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S5935QF 参数 Datasheet PDF下载

S5935QF图片预览
型号: S5935QF
PDF下载: 下载PDF文件 查看货源
内容描述: 5V PCI总线主/目标设备的32位 [PCI 5V Bus Master/Target Device 32-bit]
分类和应用: 驱动器总线控制器微控制器和处理器外围集成电路数据传输PC时钟
文件页数/大小: 190 页 / 706 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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®
MAILBOX OVERVIEW  
S5935  
FUNCTIONAL DESCRIPTION  
MAILBOX OVERVIEW  
Figure 1 shows a block diagram of the PCI to Add-On  
mailbox registers. Add-On incoming mailbox read ac-  
cesses pass through an output interlock latch. This  
prevents a PCI bus write to a PCI outgoing mailbox  
from corrupting data being read by the Add-On. Fig-  
ure 2 shows a block diagram of the Add-On to PCI  
mailbox registers. PCI incoming mailbox reads also  
pass through an interlocking mechanism. This pre-  
vents an Add-On write to an outgoing mailbox from  
corrupting data being read by the PCI bus. The fol-  
lowing sections describe the mailbox flag functionality  
and the mailbox interrupt capabilities.  
The S5935 has eight 32-bit mailbox registers. The mail-  
boxes are useful for passing command and status infor-  
mation between the Add-On and the PCI bus. The PCI  
interface has four incoming mailboxes (Add-On to PCI)  
and four outgoing mailboxes (PCI to Add-On). The Add-  
On interface has four incoming mailboxes (PCI to Add-  
On) and four outgoing mailboxes (Add-On to PCI). The  
PCI incoming and Add-On outgoing mailboxes are the  
same, internally. The Add-On incoming and PCI outgo-  
ing mailboxes are also the same, internally.  
The mailbox status may be monitored in two ways.  
The PCI and Add-On interfaces each have a mailbox  
status register to indicate the empty/full status of  
bytes within the mailboxes. The mailboxes may also  
be configured to generate interrupts to the PCI and/or  
Add-On interface. One outgoing and one incoming  
mailbox on each interface can be configured to gen-  
erate interrupts.  
Figure 1. Block Diagram - PCI to Add-On Mailbox Register  
MAILBOX  
REGISTER  
ADD-ON  
BUS  
"INCOMING  
MAILBOX"  
SELECT  
ADD-ON  
BUS  
"INCOMING MAILBOX"  
OUTPUT  
INTERLOCK  
LATCH  
OUTPUT  
DRIVER  
PCI BUS  
"OUTGOING MAILBOX"  
D
Q
D
Q
LOAD ENABLE  
EN  
EN  
ADD-ON  
RD#  
READ ENABLE  
SELECT#  
MAILBOX  
FULL  
S
"O"  
D
Q
EMPTY/FULL FF  
SELECTED READ ENABLE  
Figure 2. Block Diagram - Add-On to PCI Mailbox Register  
PCI BUS  
OUTPUT  
INTERLOCK  
LATCH  
PCI  
MAILBOX  
REGISTER  
ADD-ON  
BUS  
"OUTGOING  
MAILBOX"  
"INCOMING MAILBOX"  
"INCOMING  
MAILBOX"  
SELECT  
Q
D
Q
D
EN  
PCI READ PULSE  
WR#  
SELECT#  
ADD-ON WRITE PULSE  
MAILBOX  
FULL  
S
Q
"O"  
D
REGISTER  
DECODE OF  
ADR[6:2]  
BE[3:0]#  
EMPTY/FULL FF  
SELECTED  
READ PULSE  
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