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PCI CONFIGURATION REGISTERS
S5935
PCI CONFIGURATION REGISTERS
Each PCI bus device contains a unique 256-byte region called its configuration header space. Portions of this
configuration header are mandatory in order for a PCI agent to be in full compliance with the PCI specification.
This section describes each of the configuration space fields—its address, default values, initialization options,
and bit definitions—and also provides an explanation of its intended usage.
Table 1. Configuration Registers
Configuration
Address Offset
Abbreviation
Register Name
00h–01h
02h–03h
04h–05h
06h–07h
08h
09h–0Bh
0Ch
VID
DID
Vendor Identification
Device Identification
PCI Command Register
PCI Status Register
Revision Identification Register
Class Code Register
Cache Line Size Register
Master Latency Timer
Header Type
PCICMD
PCISTS
RID
CLCD
CALN
LAT
0Dh
0Eh
HDR
0Fh
BIST
BADR0-BADR5
—
EXROM
—
INTLN
INTPIN
MINGNT
MAXLAT
—
Built-in Self-test
Base Address Registers (0-5)
Reserved
Expansion ROM Base Address
Reserved
Interrupt Line
Interrupt Pin
Minimum Grant
Maximum Latency
Not used
10h–27h
28h–2Fh
30h
34h–3Bh
3Ch
3Dh
3Eh
3Fh
40h–FFh
3-17
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
