Revision 1.02 – June 27, 2006
S5935 – PCI Product
Data Book
This register provides the method for choosing which
conditions are to produce an interrupt on the Add-On
bus interface, a method for viewing the cause for the
interrupt, and a method for acknowledging (removing)
the interrupt’s assertion.
ADD-ON INTERRUPT CONTROL/STATUS
REGISTER (AINT)
Add-On Interrupt Control and Status
38h
Register Name
Interrupt sources:
Add-On
Address Offset
•
One of the Incoming mailboxes (1,2,3 or 4)
becomes full.
00000000h
Power-up value
Attribute
Size
•
One of the Outgoing mailboxes (1,2,3 or 4)
becomes empty.
Read/Write, Read/Write_One_Clear
32 bits
•
•
•
•
Built-in self test issued.
Write Transfer Count = zero
Read Transfer Count = zero
Target/Master Abort
Figure 35. Add-On Interrupt Control/Status Register
Interrupt Status
Interrupt Selection
Bit
0
12
8
4
16 1514
31
2423 2120191817
0 0 0 0 0 0 0 0
0
0
0 0 0
Value
Interrupt Asserted (RO)
Interrupt Source (R/W)
Enable & Selection
Bus Mastering
Error Interrupt (R/WC)
D4-D0 Incoming Mailbox
(Becomes Full)
BIST (R/WC)
D4=Enable Interrrupt
D3-D2=Mailbox #
Read Transfer
Complete (R/WC)
Write Transfer
0 0=Mailbox 1
0 1=Mailbox 2
1 0=Mailbox 3
1 1=Mailbox 4
Complete (R/WC)
Outgoing Mailbox
Interrupt (R/WC)
D0-D1=Byte #
Incoming Mailbox
Interrupt (R/WC)
0 0=Byte 0
0 1=Byte 1
1 0=Byte 2
1 1=Byte 3
D12-D8 Outgoing Mailbox (R/W)
(Goes empty)
D12=Enable Interrupt
D11-D10=Mailbox
0 0=Mailbox 1
0 1=Mailbox 2
1 0=Mailbox 3
1 1=Mailbox 4
D9-D8=Byte #
0 0=Byte 0
0 1=Byte 1
1 0=Byte 2
1 1=Byte 3
Interrupt on Write
Transfer Complete
Interrupt on Read
Transfer Complete
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DS1527
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
