Revision 1.02 – June 27, 2006
S5935 – PCI Product
FIFO OVERVIEW
Data Book
either a PCI target or program it to enable the S5935
to be a PCI initiator (bus master). The following sec-
tions describe, on a functional level, the capabilities of
the S5935 FIFO interface.
The S5935 has two internal FIFOs. One FIFO is for
PCI bus to Add-On bus, the other FIFO is for Add-On
bus to PCI bus transfers. Each of these has eight 32-
bit registers. The FIFOs are both addressed through a
single PCI/Add-On Operation Register offset, but
which internal FIFO is accessed is determined by
whether the access is a read or write.
FIFO Buffer Management and Endian Conversion
The S5935 provides a high degree of flexibility for con-
trolling the data flow through the FIFO. Each FIFO
(PCI to Add-On and Add-On to PCI) has a specific
FIFO advance condition. For FIFO writes, the byte
which signifies a location is full is configurable. For
FIFO reads, the byte which signifies a location is
empty is configurable. This ability is useful for transfer-
ring data through the FIFO with Add-Ons which are not
32-bits wide. Endian conversion may also be per-
formed on data passing through the FIFO.
The FIFO may be either a PCI target or a PCI initiator.
As a target, the FIFO allows a PCI bus master to
access Add-On data. The FIFO also allows the S5935
to become a PCI initiator. Read and write address reg-
isters and transfer count registers allow the S5935 to
perform DMA transfers across the PCI bus. The FIFO
may act as initiator and a target at different times in the
same application.
FIFO Advance Conditions
The FIFO can be configured to support various Add-
On bus configurations. FIFO status and control signals
allow simple cascading into an external FIFO, the Add-
On bus can be 8-, 16-, or 32-bits wide, and data
endian conversion is optional to support any type of
Add-On CPU. PCI and Add-On interrupt capabilities
are available to support bus mastering through the
FIFO.
The specific byte lane used to advance the FIFO,
when accessed, is determined individually for each
FIFO interface (PCI and Add-On). The control bits to
set the advance condition are D29:26 of the Interrupt
Control/Status Register (INTCSR) in the PCI Opera-
tion Registers (Figure 1). The default FIFO advance
condition is set to byte 0. With the default setting, a
write to the FIFO with BE0# asserted indicates that the
FIFO location is now full, advancing the FIFO pointer
to the next location. BE0# does not have to be the only
byte enable asserted. Note, the FIFO advance condi-
tion may be different for the PCI to Add-On FIFO and
the Add-On to PCI FIFO directions.
FUNCTIONAL DESCRIPTION
The S5935 FIFO interface allows a high degree of
functionality and flexibility. Different FIFO manage-
ment schemes, endian conversion schemes, and
advance conditions allow for a wide variety of Add-On
interfaces. Applications may implement the FIFO as
Figure 72. INTCSR FIFO Advance and Endian Control Bits
INTCSR
31 30 29 28 27 26 25 24
PCI TO ADD-ON FIFO
PCI ADD-ON DWORD
TOGGLE
0 = BYTES 0-3 (DEFAULT)
1 = BYTE 4-7 (NOTE1)
0
0
1
1
0
1
0
1
NO CONVERSION (DEFAULT)
16 BIT ENDIAN CONV.
32 BIT ENDIAN CONV.
64 BIT ENDIAN CONV
FIFO ADVANCE CONTROL
PCI INTERFACE
0
0
1
1
ADD-ON TO PCI FIFO
0 BYTE 0 (DEFAULT)
1 BYTE 1
0 BYTE 2
ADD-ON PCI
TOGGLE
DWORD
0 = BYTES 0-3 (DEFAULT)
1 = BYTE 4-7 (NOTE1)
1 BYTE 3
FIFO ADVANCE CONTROL
ADD-ON INTERFACE
0
0
1
1
0 BYTE 0 (DEFAULT)
1 BYTE 1
0 BYTE 2
1 BYTE 3
NOTE 1: D24 AND D25 MUST BE ALSO "1"
134
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