Revision 1.02 – June 27, 2006
S5935 – PCI Product
Data Book
Figure 82. Single Cycle Pass-Thru Read with PTADR# ...................................................................................... 158
Figure 83. Pass-Thru Burst Write ........................................................................................................................ 158
Figure 84. Pass-Thru Burst Writes Controlled by PTRDY# ................................................................................. 159
Figure 85. Pass-Thru Burst Read ........................................................................................................................ 161
Figure 86. PCI Burst Read Controlled by PTRDY# .............................................................................................. 163
Figure 87. Target Requested Retry on the First PCI Data Phase ........................................................................ 165
Figure 88. Target Requested Retry after the First Data Phase of a Burst Operation .......................................... 166
Figure 89. Pass-Thru Signals after a Target Requested Retry ............................................................................ 167
Figure 90. Pass-Thru Write to an 8-bit Add-On Device ........................................................................................ 169
Figure 91. PCI Clock Timing ................................................................................................................................ 176
Figure 92. PCI Output Timing .............................................................................................................................. 177
Figure 93. PCI Input Timing ................................................................................................................................. 177
Figure 94. Add-On Clock Timing .......................................................................................................................... 178
Figure 95. Pass-Thru Clock Relationship to PCI Clock ........................................................................................ 178
Figure 96. Synchronous RDFIFO# Timing ........................................................................................................... 179
Figure 97. Synchronous WRFIFO# Timing .......................................................................................................... 180
Figure 98. Asynchronous RD# FIFO Timing ........................................................................................................ 181
Figure 99. Asynchronous WR# FIFO Timing ....................................................................................................... 182
Figure 100. Synchronous RD# FIFO Timing ........................................................................................................ 183
Figure 101. Synchronous RD# FIFO Timing ........................................................................................................ 184
Figure 102. Synchronous WR# FIFO Timing ....................................................................................................... 185
Figure 103. Synchronous Multiple WR# FIFO Timing .......................................................................................... 186
Figure 104. Pass-Thru Data Register Read Timing ............................................................................................. 188
Figure 105. Pass-Thru Data Register Write Timing ............................................................................................. 188
Figure 106. Pass-Thru Status Indicator Timing ................................................................................................... 189
Figure 107. nv Memory Read Timing ................................................................................................................... 190
Figure 108. nv Memory Write Timing ................................................................................................................... 190
Figure 109. IRQ# Interrupt Output Timing ........................................................................................................... 191
Figure 110. Mailbox 4, Byte 3 Direct Input Timing ............................................................................................... 191
Figure 111. S5935 - 160 PQFP Package Drawing .............................................................................................. 197
Figure 112. S5935 - Marking Drawing ................................................................................................................. 198
Figure 113. Package Physical Dimension - 208 TQFP ........................................................................................ 202
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DS1527
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
