32-Bit PCI “MatchMaker”
S5933 P
IN
D
ESCRIPTIONS
AD[31:0]
t/s
Address/Data.
Address and data are multiplexed on the same PCI bus pins. A PCI Bus
transaction consists of an address phase followed by one or more data phases. An address
phase occurs on the PCLK cycle in which FRAME# is asserted. A data phase occurs on
the PCLK cycles in which IRDY# and TRDY# are both asserted.
Bus Command/Byte Enable.
Bus commands and byte enables are multiplexed on the same
pins. These pins define the current bus command during an address phase. During a data
phase, these pins are used as Byte Enables, with C/BE[0]# enabling byte 0 (LSB) and C/
BE[3]# enabling byte 3 (MSB).
C/BE# [3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
PAR
t/s
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
S5933
C/BE[3:0]#
t/s
Parity.
Parity is always driven as even from all AD[31:0] and C/BE[3:0]# signals. The par-
ity is valid during the clock following the address phase and is driven by the bus master.
During a data phase for write transactions, the bus master sources this signal on the clock
following IRDY# active; during a data phase for read transactions, this signal is driven by
the target and is valid on the clock following TRDY# active. The PAR signal has the same
timing as AD[31:0], delayed by one clock.
Clock.
The rising edge of this signal is the reference upon which all other signals are based
except for RST# and INTA#. The maximum PCLK frequency for the S5933 is 33 MHz
and the minimum is DC (0 Hz).
Reset
is used to bring all other signals within the S5933 to a known, consistent state. All
PCI bus interface output signals are not driven (tri-stated), and open drain signals such as
SERR# are floated.
Frame.
This signal is driven by the current bus master to indicate the beginning and dura-
tion of a bus transaction. When FRAME# is first asserted, it indicates a bus transaction is
beginning with a valid addresses and bus command present on AD[31:0] and C/BE[3:0].
FRAME# remains asserted during a burst data transfer and is deasserted to signify the
final data phase.
Initiator Ready.
This signal is always driven by the bus master to indicate its ability to
complete the current data phase. During write transactions, it indicates AD[31:0] contains
valid data. Wait states occur until both TRDY# and IRDY# are asserted together.
PCLK
in
RST#
in
FRAME#
s/t/s
IRDY#
s/t/s
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7
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
