Revision 1.02 – April 12, 2007
S5920 – PCI Product: PCI Configuration Registers
Data Book
This 16-bit register provides basic control over a
device’s ability to respond to or perform PCI accesses.
This register is defined by the PCI specification and its
implementation is required of all PCI devices. Four of
the ten implemented bits are required by the S5920;
those which are not required are hardwired to 0. The
definitions for all the fields are provided here for
completeness.
PCI COMMAND REGISTER (PCICMD)
PCI Command
Register Name:
04h-05h
0000h
Address Offset:
Power-up value:
Boot-load:
not used
Read/Write (R/W on 4 bits, R/O for
all others)
Attribute:
Size:
16 bits
Figure 9. PCI Command Register
15
9
0
8
X
7
0
6
X
5
0
4
0
3
0
2
0
1
X
0
X
Reserved = 00
Fast Back-to-Back
SERR# Enable
Wait Cycle Enable
PERR# Enable
Palette Snoop Enable
Memory Write and Invalidate Enable
Special Cycle Enable
Bus Master Enable
Memory Access Enable
I/O Access Enable
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