Revision 1.02 – April 12, 2007
S5920 – PCI Product: Mailbox Overview
Data Book
Figure 56. Add-On to PCI Mailbox Register
PCI
INCOMMING
MAILBOX
OUTPUT
INTERLOCK
REGISTER
MAILBOX
REGISTER
Q
D
Q
D
PCI BUS
ADD-ON BUS
EN
EN
EN
PCI CLK
PCI READ
ADCLK
WR#
SELECT#
ADR -MB
VDD
R
D
Q
ADCLK
MAILBOX
FULL
S
D
Q
ADCLK
Mailbox Empty/Full Conditions
13 are set. These bits indicate that outgoing mailbox
bytes 0 and 1 are full. Reading the Add-On Mailbox
Empty/Full Status Register (AMBEF) shows that bits
12 and 13 in this register are also set, indicating the
Add-On incoming mailbox bytes 0 and 1 are full. An
Add-On read of the incoming mailbox, bytes 0 and 1,
clears the status bits in both the MBEF and AMBEF
status registers.
The PCI and Add-On interfaces each have a mailbox
status register. The PCI Mailbox Empty/Full Status
(MBEF) and Add-On Mailbox Empty/Full Status
(AMBEF) registers indicate the status of all bytes
within the mailbox registers. A write to an outgoing
mailbox sets the status bits for that mailbox. The byte
enables determine which bytes within the mailbox
become full (and which status bits are set).
The read-only status flags in the MBEF and AMBEF
registers are reset when the corresponding byte is
read from the incoming mailbox. Alternately, these
flags can be globally reset from either the PCI inter-
face or the Add-On interface. The PCI Bus Reset
Control Register (RCR) and the Add-On Reset Control
Register (ARCR) each have a bit to reset all of the
mailbox status flags.
An outgoing mailbox for one interface is an incoming
mailbox for the other. Therefore, incoming mailbox sta-
tus bits on one interface are identical to the
corresponding outgoing mailbox status bits on the
other interface. The following list shows the relation-
ship between the mailbox registers on the PCI and
Add-On interfaces.
Mailbox Interrupts
PCI Interface
Add-On Interface
Incoming Mailbox
Outgoing Mailbox
The designer has the option to generate interrupts to
the PCI and Add-On interfaces when specific mailbox
events occur. The PCI and Add-On interfaces can
each define two conditions where interrupts may be
generated. An interrupt can be generated when the
incoming mailbox becomes full and/or when the outgo-
ing mailbox becomes empty. A specific byte within a
specific mailbox is selected to generate the interrupt.
The conditions defined to generate interrupts to the
PCI interface do not have to be the same as the condi-
tions defined for the Add-On interface.
Outgoing Mailbox
Incoming Mailbox
=
=
PCI Mailbox Empty/
Full
Add-On Mailbox Empty/
Full
=
A write to an outgoing mailbox also writes data into the
incoming mailbox on the other interface. It also sets
the status bits for the outgoing mailbox and the status
bits for the incoming mailbox on the other interface.
Reading the incoming mailbox clears the correspond-
ing status bit(s) in the Add-On and PCI mailbox status
registers (AMBEF and MBEF).
For the incoming mailbox interrupts, when the speci-
fied byte becomes full, an interrupt is generated. The
interrupt might be used to indicate command or status
information has been provided, and must be read. For
For example, a PCI write is performed to the PCI out-
going mailbox, writing bytes 0 and 1 (CBE0# and
CBE1# asserted). Reading the PCI Mailbox Empty/
Full Status Register (MBEF) indicates that bits 12 and
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111
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