Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Add-On Controlled Bus Master Read Transfer
Count Register (MRTC)
This register is only accessible when Add-On initiated
bus mastering is enabled.
The master read transfer count register is used to con-
vey to the PCI controller the actual number of bytes
that are to be transferred. The value in this register is
decremented with each bus master PCI read opera-
tion until the transfer count reaches zero. Upon
reaching zero, the transfer operation ceases and an
interrupt may be optionally generated to either the PCI
or Add-On bus interface. Transfers which are not
whole multiples of DWORDs in size result in a partial
word ending cycle. This partial word ending cycle is
possible since all bus master transfers for this control-
ler are required to begin on a DWORD boundary.
Master Read Transfer Count
Register Name:
Add-On Address Offset:
Power-up value:
Attribute:
5Ch
00000000h
Read/Write
32 bits
Size:
Figure 38. Add-On Controlled Bus Master Read Transfer Count Register
31
26 25
0 Bit
Value
00
Transfer Count
in Bytes (R/W)
Reserved = 0's (RO)
AMCC Confidential and Proprietary
DS1657 84
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
