Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Interrupt Control/Status Register (INTCSR)
This register provides the method for choosing which
conditions are to produce an interrupt on the PCI bus
interface, a method for viewing the cause of the inter-
rupt, and a method for acknowledging (removing) the
interrupt’s assertion.
Interrupt Control and Status
Register Name:
38h
PCI Address Offset:
Power-up value:
00000000h
Interrupt sources:
•
•
•
Write Transfer Terminal Count = zero
Read Transfer Terminal Count = zero
Read/Write (R/W), Read/
Write_One_Clear (R/WC)
Attribute:
Size:
One of the Outgoing mailboxes (1,2,3 or 4)
becomes empty
32 bits
•
One of the Incoming mailboxes (1,2,3 or 4)
becomes full.
•
•
Target Abort
Master Abort
Figure 29. Interrupt Control/Status Register
Actual Interrupt
Interrupt Selection
Bit
24 23 21
16 15 14 12
0
8
4
0
31
FIFO and Endian Control
0
0 0 0
Value
Interrupt Source (R/W)
Enable & Selection
Interrupt Asserted (RO)
Target Abort (R/WC)
Master Abort (R/WC)
D4-D0 Outgoing Mailbox
(Goes empty)
D4=Enable Interrrupt
D3-D2=Mailbox #
Read Transfer
Complete (R/WC)
0 0=Mailbox 1
0 1=Mailbox 2
1 0=Mailbox 3
1 1=Mailbox 4
Write Transfer
Complete (R/WC)
Incoming Mailbox
Interrupt (R/WC)
D1-D0=Byte #
Outgoing Mailbox
Interrupt (R/WC)
0 0=Byte 0
0 1=Byte 1
1 0=Byte 2
1 1=Byte 3
D12-D8 Incoming Mailbox (R/W)
(Becomes full)
D12=Enable Interrupt
D11-D10=Mailbox
0 0=Mailbox 1
0 1=Mailbox 2
1 0=Mailbox 3
1 1=Mailbox 4
D9-D8=Byte #
0 0=Byte 0
0 1=Byte 1
1 0=Byte 2
1 1=Byte 3
Interrupt on Write
Transfer Complete
Interrupt on Read
Transfer Complete
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