Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
PCI CONFIGURATION REGISTERS
Data Sheet
ification. This section describes each of the
configuration space fields—its address, default values,
initialization options, and bit definitions—and also pro-
vides an explanation of its intended usage.
Each PCI bus device contains a unique 256-byte
region called its configuration header space. Portions
of this configuration header are mandatory in order for
a PCI agent to be in full compliance with the PCI spec-
Table 16. Configuration Registers
Configuration Address Offset
Abbreviation
VID
Register Name
Vendor Identification
Device Identification
PCI Command Register
PCI Status Register
Revision Identification Register
Class Code Register
Cache Line Size Register
Master Latency Timer
Header Type
00h–01h
02h–03h
04h–05h
06h–07h
08h
DID
PCICMD
PCISTS
RID
09h–0Bh
0Ch
CLCD
CALN
LAT
0Dh
0Eh
HDR
0Fh
BIST
Built-in Self-test
10h–27h
28h–2Fh
30h
BADR0-BADR5
—
Base Address Registers (0-5)
Reserved
EXROM
—
Expansion ROM Base Address
Reserved
34h–3Bh
3Ch
INTLN
INTPIN
MINGNT
MAXLAT
—
Interrupt Line
3Dh
Interrupt Pin
3Eh
Minimum Grant
3Fh
Maximum Latency
Not used
40h–FFh
AMCC Confidential and Proprietary
DS1657 27
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
