Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
When the Add-On is busy completing a Pass-Thru
write, the S5335 requests an immediate retry for all
Pass-Thru region accesses, allowing the PCI bus to
perform other operations. PCI Operation Registers
may be accessed while the Add-On is still completing
a Pass-Thru access. Only Pass-Thru region accesses
receive retry requests.
tor’s data (for reads). S5335 PCI Operation Registers
may be accessed while the Add-On is still completing
a Pass-Thru access. Only other Pass-Thru region
accesses receive retry requests.
Add-On Bus Interface
The Pass-Thru address and data registers can be
accessed as Add-On operation registers. The inter-
face to the Pass-Thru registers is described in. The
Pass-Thru data register is updated on the rising edge
of BPCLK. For this reason, all Pass-Thru inputs must
be synchronous to BPCLK. In the following sections
the Add-On Pass-Thru interface is described for Pass-
Thru single cycle accesses, burst accesses, target-
requested retries, and when using 8-bit and 16-bit
Add-On data buses.
PCI Read Retries
When the S5335 requests a retry for a PCI Pass-Thru
read, it indicates that the Add-On could not complete
the read in the required time. The Pass-Thru data can-
not be read by the PCI interface until the Add-On
asserts PTRDY#, indicating the access is complete.
If the retry occurs after the Add-On has completed the
Pass-Thru operation by writing the appropriate data
into the Pass-Thru data register and asserting
PTRDY#, the S5335 asserts DEVSEL# and TRDY# to
complete the PCI read. If the Add-On still has not com-
pleted the Pass-Thru read, the S5335 waits for the
required 16 clocks. If the Add-On completes the
access during this time, TRDY# is asserted and the
access is finished. If the Add-On cannot complete the
access within 16 clocks, another retry is requested.
Single Cycle Pass-Thru Writes
A single cycle Pass-Thru write operation occurs when
a PCI initiator writes a single value to a Pass-Thru
region. PCI single cycle transfers consists of an
address phase and one data phase. During the
address phase of the PCI transfer, the S5335 stores
the PCI address into the Pass-Thru Address Register
(APTA). If the S5335 determines that the address is
within one of its defined Pass-Thru regions, it captures
the PCI data into the Pass-Thru Data Register (APTD).
When the Add-On is busy completing a Pass-Thru
read, the S5335 requests an immediate retry for all
Pass-Thru region accesses, except the region cur-
rently completing the previous access. This allows the
PCI bus to perform other operations. The next access
to the Pass-Thru region which initiated the retry must
be to the same address which caused the retry.
Another initiator accessing the same Pass-Thru region
causes the S5335 to respond with the original initia-
Figure 83 shows a single cycle Pass-Thru write
access (Add-On read). The Add-On must read the
data stored in the APTD register and transfer it to its
destination. Note: RD# may be asserted for multiple
clocks to allow interfacing with slow Add-On devices.
Data remains valid until PTRDY# is asserted.
AMCC Confidential and Proprietary
DS1657 143
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
