Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
8-Bit and 16-Bit Add-On Interfaces
The following sections discuss the registers associ-
ated with the mailboxes and accesses required for
different modes of mailbox operation.
Some Add-On designs may implement an 8-bit or 16-
bit bus interface. The mailboxes do not require a 32-bit
Add-On interface. For 8-bit interfaces, the 8-bit data
bus may be externally connected to all four bytes of
the 32-bit Add-On interface (DQ 31:24, 23:16, 15:8,
7:0 are all connected). The Add-On device reading or
writing the mailbox registers may access all mailbox
bytes by cycling through the Add-On byte enable
inputs. A similar solution applies to 16-bit Add-On
buses. This solution works for Add-Ons which always
use just 8-bit or just 16-bit accesses. If the MODE pin
is high, indicating a 16-bit Add-On interface, the previ-
ous solution may be modified for an 8-bit interface.
The difference is that ADR1 must be toggled after the
first two accesses to steer the S5335 internal data bus
to the upper 16-bits of the mailboxes.
Mailbox Status
Every byte in each mailbox has a status bit in the Mail-
box Empty/Full Status Registers (MBEF and AMBEF).
Writing a particular byte into an outgoing mailbox sets
the corresponding status bit in both the MBEF and
AMBEF registers. A read of a ‘full’ byte in a mailbox
clears the status bit. The MBEF and AMBEF are read-
only. Status bits cannot cleared by writes to the status
registers.
The S5335 allows the mailbox status bits to be reset
through software. The Bus Master Control/Status
(MCSR) PCI Operation Register and the Add-On Gen-
eral Control/Status (AGCSTS) Add-On Operation
Register each have a bit to reset mailbox status. Writ-
ing a ‘1’ to Mailbox Flag Reset bit in the MCSR or the
AGCSTS register immediately clears all bits in the
both the MBEF and AMBEF registers. Writing a ‘0’ has
no effect. The Mailbox Flag Reset bit is write-only.
CONFIGURATION
The PCI interface and the Add-On interface each have
four incoming mailboxes (IMBx or AIBMx) and four
outgoing mailboxes (OMBx or AOMBx) along with a
single mailbox status register (MBEF or AMBEF). Out-
going mailboxes are read/write, incoming mailboxes
and the mailbox status registers are read-only.
The flag bits should be monitored when transferring
data through the mailboxes. Checking the mailbox sta-
tus before performing an operation prevents data from
being lost or corrupted. The following sequences are
suggested for PCI mailbox operations using status
polling (interrupts disabled):
Reading a PCI Incoming Mailbox:
1. Check Mailbox Status. Read the mailbox status register to determine if any information has been passed from the Add-
On interface.
MBEF
Bits 31:16
If a bit is set, valid data is contained in the corresponding mailbox
byte.
2. Read Mailbox(es). Read the mailbox bytes which MBEF indicates are full. This automatically resets the status bits in
the MBEF and AMBEF registers.
IMBx
Bits
31:0 Mailbox data.
Writing a PCI Outgoing Mailbox:
1. Check Mailbox Status. Read the mailbox status register to determine if information previously written to the mailbox has
been read by the Add-On interface. Writes to full mailbox bytes overwrite data currently in the mailbox (if not already
read by the Add-On interface). Repeat until the byte(s) to be written are empty.
MBEF Bits 15:0 If a bit is set, valid data is contained in the corresponding mailbox byte and has not been read by the
Add-On.
2. Write Mailbox(es). Write to the outgoing mailbox byte(s).
OMBx Bits 31:0 Mailbox data.
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