Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Mailbox Interrupts
(TRDY# asserted). A FIFO status change caused by
an Add-On FIFO access is reflected immediately (after
a short propagation delay) after the access occurs. For
Add-On accesses, FIFO status is updated after the ris-
ing edge of BPCLK for synchronous interfaces or after
the rising edge of the read or write strobe for asyn-
chronous interfaces.
Mailboxes can be configured to generate Add-On
interrupts (IRQ#) and/or allow the Add-On to generate
PCI interrupts (INTA#). Mailbox empty/full status con-
ditions be can used to interrupt the Add-On or PCI
host to indicate some action is required. An individual
mailbox byte is selected to generate an interrupt when
accessed. An outgoing mailbox becoming empty or an
incoming mailbox becoming full asserts the interrupt
output (if enabled).
FIFO Control Signals
For Add-On initiated PCI bus mastering, the FIFO sta-
tus reset controls FWC# (Add-On to PCI FIFO clear)
and FRC# (PCI to Add-On FIFO clear) are available.
FWC# and FRC# must be asserted for a minimum of
one BPCLK period to be recognized. These inputs are
sampled at the rising edge of BPCLK. These inputs
should not be asserted unless the FIFO is idle. Assert-
ing a FIFO status reset input during a PCI or Add-On
FIFO access results in indeterminate operation.
When used with a serial nv memory boot device, the
mailboxes also provide a way to generate PCI inter-
rupts (INTA#) through hardware. When a serial nv
memory boot device is used, the device pin functions
EA0 - EA8 are redefined. These pins then provide
direct, external access to the Add-On outgoing mail-
box 4, byte 3 (which is also PCI incoming mailbox 4,
byte 3).
For Add-On initiated bus master transfers, AMREN
(Add-On bus master read enable) and AMWEN (Add-
On bus master write enable) are used, in conjunction
with the appropriate FIFO status signals, to enable the
S5335 to assert its PCI bus request (REQ#).
FIFO BUS INTERFACE
The FIFO register on the Add-On interface may only
be accessed synchronously or asynchronously. Asyn-
chronous burst read and write FIFO operations are not
recommended. Location 45h, bits 6 and 5 in the nv
memory boot device must be programmed to a “0” for
correct operation.
PASS-THRU BUS INTERFACE
The S5335 Pass-Thru interface is synchronous. The
Add-On Pass-Thru Address (APTA) and Add-On
Pass-Thru Data (APTD) registers may be accessed
pseudo-synchronously.
FIFO Direct Access Inputs
RDFIFO# and WRFIFO# are referred to as FIFO
‘direct access’ inputs. Asserting RDFIFO# is function-
ally identical to accessing the FIFO with RD#,
SELECT#, BE[3:0]#, and ADR[6:2]. Asserting
WRFIFO# is functionally identical to accessing the
FIFO with WR#, SELECT#, BE[3:0]#, and ADR[6:2].
RD# and WR# must be deasserted when RDFIFO# or
WRFIFO# is asserted, but SELECT# may be
asserted. These inputs automatically drive the address
(internally) to 20h and assert all byte enables. The
ADR[6:2] and BE[3:0]# inputs are ignored when using
the FIFO direct access inputs. RDFIFO# and
WRFIFO# are useful for Add-On designs which cas-
cade an external FIFO into the S5335 FIFO or use
dedicated external logic to access the FIFO.
Although BPCLK is used to clock data into and out of
the Pass-Thru registers, accesses may be performed
asynchronously. For reads, APTA or APTD data
remains valid as long as RD# (or PTADR#) is
asserted. A new value is not driven until PTRDY# is
asserted by Add-On logic. For writes to APTD, data is
clocked into the S5335 on every BPCLK rising edge,
but is not passed to the PCI bus until PTRDY# is
asserted. PTRDY# must by synchronized to BPCLK.
Pass-Thru Status Indicators
The Pass-Thru status indicators indicate that a Pass-
Thru access is in process and what action is required
by the Add-On logic to complete the access. All Pass-
Thru status indicators are synchronous with the PCI
clock.
Direct access signals always access the FIFO as 16-
bits or 32-bits, whatever the MODE pin is configured
for. For 16-bit mode, two consecutive accesses fill or
empty the 32-bit FIFO register.
Pass-Thru Control Inputs
Some Pass-Thru implementations may require an
address corresponding to the Pass-Thru data. The
Add-On Pass-Thru Address Register (APTA) contains
the PCI address for the Pass-Thru cycle. To allow
access to the Pass-Thru address without generating
an Add-On read cycle, PTADR# is provided. PTADR#
is a direct access input for the Pass-Thru address.
FIFO Status Signals
The FIFO Status signals indicate to the Add-On logic
the current state of the S5335 FIFO. A FIFO status
change caused by a PCI FIFO access is reflected one
PCI clock period after the PCI access is completed
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