Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Targets selected with LOCK# deasserted during the
assertion of FRAME# (clock period 1 of Figure 61),
which encounter the assertion of LOCK# during the
following clock (clock period 2 of Figure 61) are there-
after considered “locked.” A target, once locked,
requires that subsequent accesses to it deassert
LOCK# while FRAME# is asserted. Figure 62 show a
subsequent access to a locked target by the master
which locked it. Because LOCK# is owned by a single
master, only that master is able to deassert it at the
beginning of a transaction (allowing successful access
to the locked target). A locked target can only be
unlocked during the clock period following the last data
transfer of a transaction when the LOCK# signal is
deasserted.
An unlocked target ignores LOCK# when it observes
that LOCK# is already asserted during the first clock
period of a transaction. This allows other masters to
access other (unlocked) targets. If an access to a
locked target is attempted by a master other than the
one that locked it, the target responds with a retry
request, as shown in Figure 63.
The S5335 responds to and supports bus masters
which lock it as a target. When the S5335 is a bus
master, it never attempts to lock a target, but it honors
a target’s request for retry if that target is locked by
another master.
Figure 62. Access to a Locked Target by its Owner
2
3
1
4
5
PCI CLOCK
FRAME #
LOCK #
(I)
(I)
(I)
DATA
DATA
AD [31:0]
IRDY#
ADDRESS
(T)
(T)
TRDY#
DEVSEL#
LOCKED
TARGET
IDENTIFIES
OWNER
CONDITION
WHICH
UNLOCKS
TARGET
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
Figure 63. Access Attempt to a Locked Target
3
2
1
4
5
PCI CLOCK
(I)
(I)
FRAME #
LOCK #
AD [31:0]
IRDY#
ADDRESS
DATA
(I)
(T)
(T)
TRDY#
DEVSEL#
STOP#
(T)
LOCKED
TARGET IDENTIFIES
THAT BUS MASTER
IS NOT ITS OWNER
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
CAUSES TARGET
RETRY TERMINATION
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DS1657 105
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
