Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Master Abort
If DEVSEL# is not asserted, the S5335 deasserts
FRAME# (if asserted) upon the sixth clock period (Fig-
ure 54). IRDY# is deasserted by the S5335 during the
next clock. The occurrence of a master abort causes
the S5335 to set bit 13 (Master Abort) of the PCI Sta-
tus Register, indicating an error condition.
PCI accesses to nonexistent or disabled targets never
observe DEVSEL# being asserted. In this situation, it
is necessary for the initiator to abort the transaction
(master abort). As an initiator, S5335 waits for six
clock periods after asserting FRAME# to determine
whether a master abort is required. These six clock
periods allow slow targets, which may require several
bus clocks before being able to assert DEVSEL#, to
respond. It is also possible a PCI bridge device is
present which employs “subtractive” decoding. A
device which does a subtractive decode asserts
DEVSEL#, claiming the cycle, when it sees that no
other device has asserted it three clocks after the
address phase.
Target-Initiated Termination
There are situations where the target may end a trans-
fer prematurely. This is called “target-initiated
termination.” Target terminations fall into three catego-
ries: disconnect, retry, and target abort. Only the
disconnect termination completes a data transfer.
Figure 54. Master Abort, No Response
4
1
2
3
5
67
8
PCI CLOCK
FRAME #
IRDY#
(I)
(I)
(T)
(T)
TRDY#
DEVSEL#
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
MEDIUM
DEVICE
FAST
DEVICE
SLOW
DEVICE
BRIDGE
DEVICE
(SUBTRACTIVE
DECODE)
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