Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Maximum Latency Register (MAXLAT)
This register may be optionally used by bus masters to
specify how often this device needs PCI bus access. A
value of zero indicates that the bus master has no
stringent requirement. The units defined by the least
significant bit are in 250-ns increments. This register is
treated as “information only” and has no further imple-
mentation within this device. Values other than zero
are possible when an external boot memory is used.
Maximum Latency
Register Name:
Address Offset:
Power-up value:
Boot-load:
3Fh
00h
External nvRAM offset 7Fh
Read Only
Attribute:
8 bits
Size:
Figure 23. Maximum Latency Register
7
0
6
5
4
3
0
2
0
1
0
0
0
bit
value
0
0
0
Value x 250ns (RO)
00-no requirement
01-FFh
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DS1657 54