Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Add-On Incoming Mailbox Registers (AIMBx) ................................................................................................. 71
Add-On Outgoing Mailbox Registers (AOMBx) ............................................................................................... 71
Add-On FIFO Register Port (AFIFO) ............................................................................................................... 71
Add-On Controlled Bus Master Write Address Register (MWAR) ................................................................... 72
Add-On Pass-Thru Address Register (APTA) ................................................................................................. 73
Add-On Pass-thru Data Register (APTD) ........................................................................................................ 73
Add-On Controlled Bus Master Read Address Register (MRAR) ................................................................... 74
Add-On Empty/Full Status Register (AMBEF) ................................................................................................. 75
Add-On Interrupt Control/status Register (AINT) ............................................................................................. 77
Add-On General Control/status Register (AGCSTS) ....................................................................................... 80
Add-On Controlled Bus Master Write Transfer Count Register (MWTC) ........................................................ 83
Add-On Controlled Bus Master Read Transfer Count Register (MRTC) ......................................................... 84
INITIALIZATION .................................................................................................................................................... 85
PCI RESET ............................................................................................................................................................ 85
LOADING FROM BYTE-WIDE NV MEMORIES ................................................................................................... 85
LOADING FROM SERIAL NV MEMORIES .......................................................................................................... 86
PCI BUS CONFIGURATION CYCLES .................................................................................................................. 88
EXPANSION BIOS ROMS .................................................................................................................................... 90
PCI BUS INTERFACE ........................................................................................................................................... 92
PCI BUS TRANSACTIONS ................................................................................................................................... 92
PCI Burst Transfers ............................................................................................................................................. 94
PCI Read Transfers ......................................................................................................................................... 94
PCI Write Transfers ......................................................................................................................................... 96
Master-Initiated Termination ............................................................................................................................ 97
Normal Cycle Completion ................................................................................................................................ 97
Initiator Preemption ......................................................................................................................................... 98
Master Abort .................................................................................................................................................... 99
Target-Initiated Termination ............................................................................................................................ 99
Target Disconnects ........................................................................................................................................ 100
Target Requested Retries ............................................................................................................................. 101
Target Aborts ................................................................................................................................................. 101
PCI BUS MASTERSHIP ...................................................................................................................................... 103
Bus Mastership Latency Components ........................................................................................................... 103
Bus Arbitration ............................................................................................................................................... 103
Bus Acquisition .............................................................................................................................................. 104
Target Latency ............................................................................................................................................... 104
Target Locking ............................................................................................................................................... 104
PCI BUS INTERRUPTS ...................................................................................................................................... 106
PCI BUS PARITY ERRORS ................................................................................................................................ 106
ADD-ON BUS INTERFACE ................................................................................................................................. 107
ADD-ON OPERATION REGISTER ACCESSES ................................................................................................ 107
Add-On Interface Signals .............................................................................................................................. 107
System Signals .............................................................................................................................................. 107
Register Access Signals ................................................................................................................................ 107
Asynchronous Register Accesses ................................................................................................................. 108
Synchronous FIFO and Pass-Thru Data Register Accesses ........................................................................ 108
nv Memory Accesses Through the Add-On General Control/Status Register ............................................... 108
AMCC Confidential and Proprietary
DS1657
4
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
