Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Figure 92. Pass-Thru Signals after a Target Requested Retry
STOP#
BPCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
1
0h
Fh
PTBE[3:0]#
SELECT#
ADR[6:2]
BE[3:0]#
2Ch
0h
RD#
DQ[31:0]
Data
PTRDY#
Internal byte lane steering may be used whether the
MODE input defines a 16-bit or 32-bit Add-On inter-
face. When a 16-bit Add-On interface is used, the
ADR1 input is used in conjunction with the byte
enables to steer data into the proper APTD register
byte locations.
When a read is performed with a BEn# input asserted,
the corresponding PTBEn# output is deasserted. Add-
On logic cycles through the byte enables to read the
entire APTD register. Once all data is read
(PTBE[3:0]# are deasserted), PTRDY# is asserted by
the Add-On, completing the access.
If MODE defines a 16-bit interface, only 16-bits of
address are driven when PTADR# is asserted. If more
than 16-bits of address are required, the Pass-Thru
Address Register (APTA) must be read with
SELECT#, RD#, byte enable and address inputs. Two
consecutive reads are required to latch all of the
address information (one with ADR1=0, one with
ADR1=1).
For Pass-Thru reads (Add-On APTD writes), the bytes
requested by the PCI initiator are indicated by the
PTBE[3:0]# outputs. Add-On logic uses the
PTBE[3:0]# signals to determine which bytes must be
written (and which bytes have already been written).
For example, a PCI initiator performs a byte Pass-Thru
read from an 8-bit Pass-Thru region with PCI BE2#
asserted. On the Add-On interface, PTBE2# is
asserted, indicating that the PCI initiator requires data
in this byte. Once the Add-On writes APTD, byte 2,
PTBE2# is deasserted, and the Add-On may assert
PTRDY#, completing the cycle.
Regardless of MODE, various data widths may be
used. For Pass-Thru writes (Add-On APTD reads),
Add-On logic must read the APTD register one byte or
one word at a time (depending on the Add-On bus
width). The internal data bus is steered to the correct
portion of APTD using the BE[3:0]# inputs. Figure 57
shows the byte lane steering mechanism used by the
S5335. The BYTEn symbols indicate data bytes in the
Pass-Thru Data Register.
Figure 58 shows how the external Add-On data bus is
steered to the Pass-Thru Data Register bytes. This
mechanism is determined by the Pass-Thru region
bus width defined during initialization (see Section
12.3). The BYTEn symbols indicate data bytes in the
Pass-Thru Data Register. For example, an 8-bit Add-
On write with BE1# asserted results in the data on
DQ[7:0] being steered into BYTE1 of the APTD
register.
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