Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Figure 83. Single Cycle Pass-Thru Write
0
1
2
3
4
5
BPCLK
PTA TN#
PTBURST#
PTNUM[1:0]
PTWR
1
PTBE[3:0]#
SELECT#
ADR[6:2]
BE[3:0]#
RD#
0h
2Ch
0h
DQ[31:0]
PT DA TA
PTRDY#
PCI Write cycle completed
Note:
For all Add-On accesses using PTADR for address data when in 16 bit mode, ADR[1] must be held low to get the low address word.
AMCC Confidential and Proprietary
DS1657 144