Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Table 62. Add-On Bus Signals
Signal
ERD#/SCL
Type
Direction
Max
0.5
Units
mA
Notes
-
Output
Bi-directional
EWR#/SDA
t/s
0.5
mA
AC CHARACTERISTICS
PCI Bus Timing
Table 63. PCI Bus Timing
Functional Operation Range (V = 3.3V ±5%, 0°C to 70°C, 10 pF load on outputs)
CC
Symbol
Parameter
Min
30
Max
Units
ns
Notes
TCL
Cycle Time
High Time
-
-
t
11
ns
1
t
Low Time
11
1
-
ns
ns
ns
ns
2
t
Rise Time (0.2V
to 0.6V
)
4
4
3
CC CC
t
Fall Time (0.6V
CC
to 0.2V
)
CC
1
4
5
t
Output Valid Delay (Bussed Signals)
Output Valid Delay (Point-to-Point Signals)
2
2
11
12
Note 1
t
t
t
Float to Active Delay
Active to Float Delay
2
-
-
ns
ns
ns
6
7
8
28
Rising Edge Setup (Bussed Signals)
Rising Edge Setup (GNT#)
Rising Edge Setup (REQ#)
7
10
12
-
-
-
t
Hold from PCI Clock Rising Edge
PCICLK to BPCLK Delay
0
2
-
ns
ns
9
t
7
10
Note:
1. Minimum times are for unloaded outputs, maximum times are for 10 pF equivalent loads.
Figure 94. PCI Clock Timing
t
t
t
1
3
4
V
IH2
0.6VCC
0.6VCC
0.2VCC
t
2
TCL
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