Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Table 57. Byte Lane Steering for Pass-Thru Data Register Read (PCI Write)
Byte Enables
APTD Register Read Byte Lane Steering
3
x
x
x
0
2
x
x
0
1
1
x
0
1
1
0
0
1
1
1
DQ[31:24]
BYTE3
BYTE3
BYTE3
BYTE3
DQ[23:16]
BYTE2
BYTE2
BYTE2
BYTE3
DQ[15:8]
BYTE1
BYTE1
BYTE3
BYTE3
DQ[7:0]
BYTE0
BYTE1
BYTE2
BYTE3
Table 58. Byte Lane Steering for Pass-Thru Data Register Write (PCI Read)
Defined
PT-Bus Width
APTD Register Write Byte Lane Steering
BYTE2 BYTE1
DQ[23:16] DQ[15:8]
BYTE3
DQ[31:24]
DQ[15:8]
DQ[7:0]
BYTE0
32-Bit Data Bus
16-Bit Data Bus
8-Bit Data Bus
DQ[7:0]
DQ[7:0]
DQ[7:0]
DQ[7:0]
DQ[7:0]
DQ[15:8]
DQ[7:0]
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