Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
5. Define PCI to Add-On and Add-On to PCI FIFO
priority. These bits determine which FIFO has pri-
ority if both meet the defined condition to request
the PCI bus. If these bits are the same, priority
alternates, with read accesses occurring first.
This must be programmed through the PCI
interface.
8. Enable Bus Mastering. Once steps 1-7 are com-
pleted, the FIFO may operate as a PCI bus
master. Read and write bus master operation
may be independently enabled or disabled. The
AMREN and AMWEN inputs control bus master
enabling for Add-On initiated bus mastering. The
MCSR bus master enable bits are ignored for
Add-On initiated bus mastering.
It is recommended that bus mastering be enabled as
the last step. Some applications may choose to leave
bus mastering enabled (AMREN and AMWEN
asserted) and start transfers by writing a non-zero
value to the transfer count registers (if they are
enabled).
MCSR
MCSR
Bit 12 Read vs. write priority
Bit 8 Write vs. read priority
6. Define transfer source/destination address.
These registers are written with the first address
that is to be accessed by the S5335. These
address registers are updated after each access
to indicate the next address to be accessed.
Transfers must start on DWORD boundaries.
If interrupts are enabled, an Add-On CPU interrupt
service routine is also required. The service routine
determines the source of the interrupt and resets the
interrupt. As mailbox registers may also be configured
to generate interrupts, the exact source of the interrupt
is indicated in the Add-On Interrupt Control Register
(AINT). Typically, the interrupt service routine is used
to setup the next transfer by writing new addresses
and transfer counts (if enabled), but some applications
may also require other actions. If read transfer or write
transfer complete interrupts are enabled, the master/
target abort interrupt is automatically enabled. These
indicate a transfer error has occurred. Writing a one to
these bits clears the corresponding interrupt.
MWAR All Bus master write address
MRAR All Bus master read address
7. Define transfer byte counts. These registers are
written with the number of bytes to be transferred.
The transfer count does not have to be a multiple
of four bytes. These registers are updated after
each transfer to reflect the number of bytes
remaining to be transferred. If transfer counts are
disabled, these registers do not need to be
programmed.
AINT Bit 21 Master/target abort caused interrupt
AINT Bit 19 Read transfer complete caused interrupt
AINT Bit 18 Write transfer complete caused interrupt
MWTC
MRTC
All
All
Write transfer byte count
Read transfer byte count
AMCC Confidential and Proprietary
DS1657 139
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
