Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Memory Device Requirements for Write Accesses
Timing
Write cycle time
Spec.
T = 30 ns
Note 1
30 ns
8T
T(max)
Address valid to write active
Data valid to write inactive
Data hold from write inactive
Write pulse width
6T+10(max)
T(max)
190 ns
30 ns
6T(max)
Note 2
180 ns
2 ns
Write inactive
Figure 70. nv Memory Write Operation
t
42
t
43
EWR#
t
44
(OUTPUT)
t
39
t
38
EA[15:0]
Address Valid
Data Valid
(OUTPUT)
t
t
46
45
EQ[7:0]
(OUTPUT)
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