Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Target Disconnects
deasserting FRAME# on the following clock but does
not complete the data transfer until IRDY# is asserted.
This situation can only occur when the S5335 is a tar-
get. When the S5335 is an initiator, IRDY# is always
asserted during the data phase (no initiator wait
states). The timing diagram in Figure 56 applies to the
S5335 as either a target disconnecting or an initiator
with its target performing a disconnect. The S5335
performs a target disconnect if a burst access is
attempted to the PCI Operation Registers.
There are many situations where a target may discon-
nect. Slow responding targets may disconnect to
permit more efficient (faster) devices to be accessed
while they prepare for the next data phase, or a target
may disconnect if it recognizes that the next data
phase in a burst transfer is out of its address range. A
target disconnects by asserting STOP#, TRDY#, and
DEVSEL# as shown in Figures 55 and 56. The initiator
in Figure 55 responds to the disconnect condition by
Figure 55. Target Disconnect Example 1 (IRDY# deasserted)
3
2
1
PCI CLOCK
FRAME #
IRDY#
(I)
(I)
(T)
(T)
TRDY#
STOP#
(T)
DEVSEL#
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
DATA
TRANSFERRED
TARGET DISCONNECT
IDENTIFIED
Figure 56. Target Disconnect Example 2 (IRDY# asserted)
2
3
1
PCI CLOCK
(I)
FRAME #
(I)
IRDY#
(T)
TRDY#
(T)
STOP#
(T)
DEVSEL#
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
DATA
TARGET DISCONNECT
TRANSFERRED SIGNALED, DATA TRANSFERRED
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