BOARD LAYOUT
Test Capabilities
TESTEN allows the chip to use the REFCLK input
instead of the VCO output to clock the chip. This is
used during chip test to allow the counters and con-
trol logic to be tested independently of the VCO. In
addition, when TESTEN is brought High, an internal
RESET pulse is generated. This initializes the inter-
nal counter flip-flops to zeros, and at the end of the
next clock cycle, the outputs go to a zero state.
TESTEN can also be used for board testing to allow
the user to control the output clocks from the S4406
by inputting the board clock to the REFCLK input.
Table 2. VCO Operating Frequencies
xFOUT0–2
66.6 MHz
50 MHz
40 MHz
33.3 MHz
25 MHz
20 MHz
S4406
tors capable of handling 25 mA. The recommended
value for the inductors is in the range from 5 to
100µH, and depends upon the frequency spectrum of
the digital power supply noise.
Decoupling capacitors are also very important to mini-
mize noise. The decoupling capacitors must have low
lead inductance to be effective, so ceramic chip capaci-
tors are recommended. Decoupling capacitors should
be located as close to the power pins as physically
possible. And the decoupling should be placed on the
top surface of the board between the part and its con-
nections to the power and ground planes.
BOARD LAYOUT CONSIDERATIONS
• The S4406 chips are sensitive to noise on the Ana-
log +5 V and Filter pins. Care should be taken during
board layout for optimum results.
• All decoupling capacitors (C1–C4 = 0.1
µF)
should
be bypassed between VCC and GND, and placed as
close to the chip as possible (preferably using ce-
ramic chip caps) and placed on top of board between
S4406 and the power and ground plane connections.
• No dynamic signal lines should pass through or
beneath the filter circuitry area (enclosed by dashed
lines in Figure 5) to avoid the possibility of noise due
to crosstalk.
• The analog VCC supply can be a filtered digital
VCC supply as shown below. The ferrite beads or
inductors, FB1 and FB2, should be placed within
three inches of the chip.
• The analog VCC plane should be separated from
the digital VCC and ground planes by at least 1/8
inch.
Figure 5. Board Layout
VCO
FREQ
266 MHz
200 MHz
160 MHz
266 MHz
200 MHz
160 MHz
MIN PHASE
DELAY
3.750 ns
5.000 ns
6.250 ns
3.750 ns
5.000 ns
6.250 ns
The bank containing the output used as feedback
must be in one of the f/2 modes to ensure the VCO is
operating within its 160-266 MHz range.
Power Supply Considerations
Power for the analog portion of the S4406 chips must
be isolated from the digital power supplies to mini-
mize noise on the analog power supply pins. This
isolation between the analog and digital power sup-
plies can be accomplished with a simple external
power supply filter (Figure 4). The analog power
planes are connected to the digital power planes
through single ferrite beads (FB1 and FB2) or induc-
Figure 4. External Power Supply Filter
D GND
A GND
45
0.1µF
FB2
D +5V
FB1
0.1µF
FB1
ANALOG +5V
0.1 µF
S4406
DIGITAL +5V
10 µF
Tantalum
(optional)
DIGITAL GND
44
43
42
1.5KΩ
A +5V
FB2
ANALOG GND
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
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