®
DEVICE SPECIFICATION
12-OUTPUT BiCMOS PLL CLOCK GENERATOR
FEATURES
• Generates outputs from 10 MHz to 66 MHz
• Four groups of three outputs (12 outputs total)
• Eight user-selectable output functions for each
group
• TTL compatible outputs, with <1.5-ns edge rates
• Performs clock doubling, dividing, invert, lead/lag
placement
• Internal VCO running between 160 to 266 MHz
• 1.0µ BiCMOS technology
• Output skew less than 500 ps
• 52 PQFP package
S4406
GENERAL DESCRIPTION
The S4406 BiCMOS clock generator provides 12 TTL
outputs with less than 500 ps of skew. Implemented
in AMCC’s 1.0µ BiCMOS technology, the internal
PLL and divider/delay selector logic allow the user to
individually tailor the (4) TTL output groups to the
system’s needs. The internal VCO can operate be-
tween 160 to 266 MHz, and the programmability al-
lows the user to generate output clocks in the 20–66
MHz range.
The S4406 offers the user the ability to select the
appropriate phase and frequency relationship for
each of the four groups of three TTL clock outputs.
In addition to clock doubling and inversion functions,
the S4406 allows any output groups to lead or lag the
others by the minimum phase delay of 3.75–6.25 ns.
APPLICATIONS
• High-performance microprocessor systems
• CMOS ASIC systems
• Backplane clock deskew and distribution
• Compatible with Intel’s Pentium™ processor
Figure 1. S4406 Block Diagram
REFCLK
PHASE
DETECTOR
CHARGE
PUMP
FBCLK
FILTER
VCO
÷2
I
0
I
1
DIVIDE
BY 2 OR 4
DELAY
GENERATION
LOGIC
MUX
TSTEN
S
Digital
+5V
0V
0 MS2,1,0
3
0 FOUT 0
MODE
SELECTION 1
disable
0 FOUT 1
0 FOUT 2
1 FOUT 0
1 MS2,1,0
Analog
+5V
0V
2 MS2,1,0
3
MODE
SELECTION 2
disable
1 FOUT 1
1 FOUT 2
2 FOUT 0
3
MODE
SELECTION 3
disable
2 FOUT 1
2 FOUT 2
3 FOUT 0
3 MS2,1,0
3
MODE
SELECTION 4
disable
3 FOUT 1
3 FOUT 2
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
