BiCMOS PLL CLOCK GENERATOR
Table 4. AC Specifications
S4402/3-66
Symbol
f
VCO
f
REF
MPW
REF
t
PE
t
PED
t
SKEW
t
DC
f
FOUT
f
HFOUT
f
2XFOUT
t
PS
t
PSJ
t
OFD
t
OFE
t
IRF
t
ORF
t
LOCK
t
j
1.
2.
3.
4.
5.
6.
7.
8.
S4402/S4403
S4402/3-80
Min
160
10
6.0
Description
VCO Frequency
REFCLK Frequency
REFCLK Minimum Pulse Width
Phase Error between REFCLK and FBCLK
Phase Error Difference from Part to Part
1
Output Skew
2
Output Duty Cycle
3
FOUT Frequency
4
HFOUT Frequency
4
2XFOUT Frequency
4
Nominal Phase Shift Increment
Phase Shift Variation
5
Tpd OUTEN0–2 to FOUTs, Disable
Tpd OUTEN0–2 to FOUTs, Enable
Input Rise/Fall Time
FOUT Rise/Fall Time
6
Loop Acquisition Time
7
Clock Stability
8
Min
160
10
7.0
-1.0
0
0
45
20
10
40
3.75
-250
2
2
1
0.5
Max
266
66
Max
320
80
Units
MHz
MHz
ns
0
750
400
55
66
33
66
6.25
+250
7
7
3
1.5
5
500
-1.0
0
0
45
20
10
40
3.125
-250
2
2
1
0.5
0
750
400
55
80
40
80
6.25
+250
7
7
3
1.5
5
500
ns
ps
ps
%
MHz
MHz
MHz
ns
ps
ns
ns
ns
ns
ms
ps
Difference in phase error between two parts at the same voltage, temperature and frequency.
Output skew guaranteed for equal loading at each output.
Outputs loaded with 35pF, measured at 1.5V.
C
LOAD
= 35 pF.
All phase shift increments and variation are measured relative to FOUT0 at 1.5V.
With 35 pF output loading (0.8 V to 2.0 V transition).
Depends on loop filter chosen. (Number given is for example filter.)
Clock period jitter with all FOUT outputs operating at 66 MHz and loaded with 25pF using loop filter
shown. Parameter guaranteed, but not tested.
Figure 5. Timing Waveforms
MPW
REF
REFCLK
MPW
REF
t
PE
t
PE
FBCLK
t
SKEW
FOUT0–3
HFOUT, X2FOUT
FOUT0–3
HFOUT, X2FOUT
t
SKEW
Output
Valid
t
OFD
Disabled
t
OFE
OUTEN0–2
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Page 9
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