BiCMOS PLL CLOCK GENERATOR
Table 3. Output Select Matrix
Configuration
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
S4402/S4403
Select Pins
PHSEL1 PHSEL0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
Output Fed
to FBCLK
FOUT0–FOUT3
HFOUT
X2FOUT (÷8)
FOUT0
FOUT1
FOUT2
FOUT3
HFOUT
X2FOUT (÷8)
FOUT0
FOUT1
FOUT2
FOUT3
HFOUT
X2FOUT (÷8)
FOUT0
FOUT1
FOUT2
FOUT3
HFOUT
X2FOUT (÷8)
Output Phase Relationships
FOUT0 FOUT1
0
2(0)
0/2
0
–Q
–2Q
–3Q
2(0)
0/2
0
t
–t
–Q
2(0)
0/2
0
–t
–2t
–3t
2(0)
0/2
0
2(0)
0/2
Q
0
–Q
–2Q
2(Q)
Q/2
–t
0
–2t
–Q–t
2(–t)
–t/2
t
0
–t
–2t
2(t)
t/2
÷
4
0
2(0)
0/2
3Q
2Q
Q
0
2(3Q)
3Q/2
Q
Q+t
Q–t
0
2(Q)
Q/2
3t
2t
t
0
2(3t)
3t/2
0/2
0
0/4
0/2
–Q/2
–2Q/2
–3Q/2
0
0/4
0/2
t/2
–t/2
–Q/2
0
0/4
0/2
–t/2
–2t/2
–3t/2
0
0/4
0
2(0)
0
–Q
–2Q
–3Q
2(0)
0
t
–t
–Q
2(0)
0
–t
–2t
–3t
2(0)
÷
8
2(0)
4(0)
0
2(0)
2(–Q)
2(–2Q)
2(–3Q)
4(0)
0
2(0)
2(t)
2(–t)
2(–Q)
4(0)
0
2(0)
2(–t)
2(–2t)
2(–3t)
4(0)
0
FOUT2 FOUT3 HFOUT
0
2(0)
0/2
2Q
Q
0
–Q
2(2Q)
2Q/2
t
2t
0
–Q+t
2(t)
t/2
2t
t
0
–t
2(2t)
2t/2
X2FOUT
Notes: 1.
2.
3.
4.
5.
6.
“0” implies the output is aligned with REFCLK.
“t” implies the output lags REFCLK by a minimum phase delay.
“Q” implies the output lags REFCLK by 90° of phase
“–t” implies the output leads REFCLK by a minimum phase delay.
“–Q” implies the output leads REFCLK by 90° of phase.
“2( )” implies the output is at twice the frequency of REFCLK.
Legend
Table
entry
Table
entry
Table
entry
Waveform
Waveform
Waveform
REFCLK
0
t
2t
–t
–t 0 t 2t
REFCLK
Q
2Q
–Q
REFCLK
2(0)
0/2
4(0)
0/4
–90° 0° 90° 180°
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Page 5
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