BiCMOS PLL CLOCK GENERATOR
S4402/S4403
• No dynamic signal lines should pass through or
beneath the filter circuitry area (enclosed by dashed
lines in Figure 6) to avoid the possibility of noise due
to crosstalk.
BOARD LAYOUT CONSIDERATIONS
• The S4402/S4403 chips are sensitive to noise on
the Analog +5 V and Filter pins. Care should be
taken during board layout for optimum results.
• The analog VCC supply can be a filtered digital
VCC supply as shown below. The ferrite beads or
inductors, FB1 and FB2, should be placed within
three inches of the chip.
• All decoupling capacitors (C1–C4 = 0.1 µF) should
be bypassed between VCC and GND, and placed as
close to the chip as possible (preferably using ce-
ramic chip caps) and placed on top of board between
S4402/S4403 and the power and ground plane con-
nections.
• The analog VCC plane should be separated from
the digital VCC and ground planes by at least 1/8
inch.
Figure 6. Board Layout (S4402 shown)
+5
D
C2
3
2
1
28 27 26
25
4
5
6
A GND
24
FB2
7
8
9
23
22
21
C3
C1
C6
GND
D
10
11
20
19
16
17 18
FB1
R1
12
14 15
13
+5
+5
A
+5
D
D
C4
No signals should pass through
the area enclosed by dashed lines
Component
C1–C4
C6
Description
0.1 µF ceramic capacitor
0.1 µF ceramic capacitor
1.5 K 10% resistor
R1
FB1,FB2
Ferrite bead or inductor
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Page 10
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
