Revision NC - Oct 17, 2001
S3098 – SONET/SDH/ATM OC-192 1:16
Low Power Receiver w/CDR/Postamp
DEVICE SPECIFICATION
Table 18. External Loop Filter Components (See Figure 12, External Loop Filter)
Symbol
Description
Value
Unit
R , R
Resistor, Surface Mount, 0402
Capacitor, Surface Mount, Non-polarized, 0603 or larger
15
Ω
1
2
C
1
µF
1
Figure 5. Parallel Data Output Delay from POCLK1,2
672.3 ps
10.709 Gbps
POCLKP
(669.3125 MHz)
@ 45/55 Duty Cycle
TSU
TH
POUTP
TSU = 525 ps
TPD
TH = 525 ps
POCLK duty cycle variation = ± 74.7 ps
OIF Specification(S3098 meets and exceeds)
POUT receiving side setup/hold time for OIF compliance = ± 200 ps
TPD = 185 ps
1. When a setup time is specified on LVDS signals between an input and a clock, the setup time in picoseconds, is from the 50% point of the
input to the 50% point of the clock.
2. When a hold time is specified on LVDS signals between an input and a clock, the hold time in picoseconds, is from the 50% point of the
clock to the 50% point of the input.
Figure 6. Differential Voltage Measurement
V(+) WRT GND
Common
Mode
V
ISINGLE
Voltage
V(-) WRT GND
V(+) WRT V(-)
V
= 2 X V
ISINGLE
IDIFF
0 V
Note: WRT = with respect to.
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
