Revision NC - Oct 15, 2001
S3097 SONET/SDH/ATM OC-192
16:1 Low Power Transmitter
DEVICE SPECIFICATION
Table 4. Input Pin Assignments and Descriptions
Pin Name
Level
I/O
Pin #
Description
PIN0P
PIN0N
PIN1P
PIN1N
PIN2P
PIN2N
PIN3P
PIN3N
PIN4P
PIN4N
PIN5P
PIN5N
PIN6P
PIN6N
PIN7P
PIN7N
PIN8P
PIN8N
PIN9P
PIN9N
PIN10P
PIN10N
PIN11P
PIN11N
PIN12P
PIN12N
PIN13P
PIN13N
PIN14P
PIN14N
PIN15P
PIN15N
LVDS
I
N2
N3
P3
P4
N4
N5
P5
P6
N6
N7
P7
P8
N8
N9
P9
P10
M11
M12
N12
N13
N14
M14
L13
K13
K14
J14
H14
G14
G13
F13
F14
E14
Parallel Data Input. A 16-bit parallel, 622.08 Mbps data, (or equivalent
FEC rate) aligned to the Parallel Input Clock (PICLK). PINP/N[15] is the
most significant bit (corresponding to bit 1 of each word, the first bit trans-
mitted). PINP/N[0] is the least significant bit (corresponding to bit 16 of
each word, the last bit transmitted). PINP/N[15:0] is sampled on the rising
edge of PICLK. Internally biased and terminated with 100 Ω line-to-line.
PICLKP
PICLKN
LVDS
I
I
D14
C14
Parallel Input Clock. A 622.08 MHz or 311.04 MHz (or equivalent FEC
rate) nominally 50% duty cycle input clock to which PINP/N[15:0] is
aligned. PICLK is used to transfer the data on the PIN inputs into a hold-
ing register in the parallel-to-serial converter. Internally biased and termi-
nated with 100 Ω line-to-line.
TESTB
LVCMOS
C6
Test Mode Enable. Active Low. Set Low to provide access to the PLL
during factory production tests. Connect to V
through a 10 kΩ
CC_2.5 V
resistor for normal system operation.
REFCLKP
REFCLKN
Diff.
LVPECL
I
I
B1
C1
Reference Clock Input. Used as the reference for the internal bit clock
frequency synthesizer. Internally biased and terminated 100 Ω line-to-
line.
RSTB
LVCMOS
Analog
A7
Master Reset. Active Low. Reset input for the device. For correct reset,
this input must be asserted Low for 100 ns. During reset, PCLK does not
toggle. Connect to V
through a 10 kΩ resistor if not used.
CC_2.5 V
CAP1
CAP2
I
B4
C4
Loop Filter. Connections for external loop filter capacitor and resistors.
(See Figure 14, External Loop Filter and Table 19, External Loop Filter
Components.)
10
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