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S3078
3.3v OC-48 multi-rate CDR with FEC and Limiting Amp
General Description
The S3078 is a 3.3 V combined limiting amplifier and Clock Recovery Unit
(CRU) for multi-rate applications. The figure below shows a typical network
application.
The internal limiting amplifier provides a voltage limited signal into the CRU
for inputs down to 5 mV. It has a Loss-of-Signal (LOS) output, which can be
programmed to assert with input levels between 25 mVp-p and 60 mVp-p.
There is also an offset correction function that reduces pulse-width distortion.
The CRU is implemented using AMCC's proven on-chip Phase Locked Loop
(PLL) technology, and it can lock onto OC-48, OC-24, OC-12, GBE, FC, or OC-
3 scrambled NRZ signal with FEC capability up to 8 bytes per 255-byte block,
and recovers the clock from the data. It consists of a phase detector, a loop
filter, and a Voltage Controlled Oscillator (VCO). The phase detector
compares the phase relationship between the VCO output and the serial data
input. A loop filter converts the phase detector output into a smooth DC
voltage, and the DC voltage is input into the VCO whose frequency is varied
by this voltage.
Products
PHY/PMD
Features
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SiGe BiCMOS Technology
+3.3 V Power Supply
Integrated Limiting Amplifier
No Degradation in Jitter Tolerance down to 5 mV Input
Loss-of-Signal Detection
Supports Clock Recovery for:
- OC-48 (2488.32 Mbps) with FEC
- OC-24 (1244.16 Mbps) with FEC
- OC-12 (622.08 Mbps) with FEC
- OC-3 (155.52 Mbps) with FEC NRZ data
- Gigabit Ethernet (GBE) (1250 Mbps) with FEC
- Fibre Channel (FC) (1062.5 Mbps) with FEC
- Fibre Channel (FC) (2125 Mbps) with FEC
Lock Detect monitors frequency of incoming data
- Selectable reference frequencies
- 155.52 MHz - 166.62 MHz or
- 19.44 MHz - 20.83 MHz
Typical power 730 mW
81 Pin PBGA package and Die
S3078 - Typical Network Application
file:///C|/Documents%20and%20Settings/tamerz/Deskto...S-G16%20-%201A%20Switching%20Regulator%20Module.htm (1 of 2)6/28/2005 1:34:00 PM
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
