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DEVICE SPECIFICATION
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Multi-Rate Performance Monitor with Forward Error Correction
S3062
2 S3062 OVERVIEW
The S3062 Performance Monitor optionally performs forward error correction on any data format. If the data is in SONET/SDH
format, the S3062 implements all required features to check the data stream and allow for the extraction and insertion of the section
and line overhead bytes. It also implements Gigabit Ethernet 8B/10B monitoring of the data stream. The data stream may run at any
frequency from 155.52 to 2500Mb/s without FEC, which includes STS-3/STM-1, STS-12/STM-4, STS-48/STM-16 and Gigabit
Ethernet rates. All modes use a 16-bit parallel single-ended LVPECL data path that is compatible with the AMCC MUX/DeMUX
chipsets. The S3062 implements forward error correction, SONET/SDH section and line overhead monitoring and insertion, and
Gigabit Ethernet monitoring. The diagram in Figure 3 shows the basic building blocks of the S3062.
Figure 3 Overview Block Diagram
PASSTHRU or
Gigabit
Gigabit Ethernet
Ethernet
monitoring
data
out
Differential
&
data
in
Differential
&
FEC
decode
STS-3,12,48/
STM-1,4,16
error monitoring
and overhead
processing
FEC
encode
error
injection
2.1 Pass Through and Forward Error Correction Applications Overview
As shown in Figure 3 , data of any type may be passed through this chip without SONET/SDH or Gigabit Ethernet monitoring. The
PASSTHRU I/O pin or register bit may be used for encoding and decoding forward error correction over data, that is in neither
SONET/SDH nor Gigabit Ethernet format. In this mode of operation the performance monitors are turned OFF to reduce power
consumption. PASSTHRU will have to be deselected to resume any performance monitoring functions regardless of the RATESEL
settings. The differential and FEC encoder/decoder may also be turned OFF to further reduce the S3062’s power consumption.
The FEC function is implemented with a variable-rate Reed Solomon codec based upon the Galois Field (28) symbols. Code rate and
error correcting capability are selectable from rate = 238/255, 8 byte errors correctable, to rate = 248/255, 3 byte correctable. Error
statistics are collected for a variety of conditions including total corrected bit errors, corrected ones, corrected zeros and
uncorrectable blocks. The codec implementation encompasses the ITU G.975 recommendation for codec and rate, interleaved to
four levels. A programmable frame synchronization byte is inserted for rapid and reliable acquisition of the coding frame boundary.
To select the pass-through mode, assert the PASSTHRU I/O signal pin or its corresponding register bit (the Micro Present byte
should be loaded with a value of 59h for the register bit to take affect). FEC encoding/decoding may be enabled by asserting the
FEC_ENC/FEC_DEC I/O pins. The FEC_ENC/FEC_ DEC I/O pins are ANDed with the complement of the associated FEC
encoding/decoding register bits when the Micro Present byte is loaded with a value of 59h. Thus, the FEC encoder/decoder may
only be enabled if the I/O pins are tied high.
NOTE: Pass-through mode has priority over all modes of operation (except differential and FEC encoding/decoding) and will
negate their selection if pass-through mode is enabled. See sections 3.3.2.14 and 3.3.2.15 for a transmit multiplexer priority listing.
Applied Micro Circuits Corporation
6290 Sequence Drive, San Diego, CA
(858) 450 9333
Revision D
CONFIDENTIAL
November 29, 2000
Page 10 of 136
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
