®
DEVICE
SPECIFICATION
2.488 GBPS – 2.7 GBPS QUAD MUX WITH FAN OUT BUFFERS
2.488 GBPS – 2.7 GBPS QUAD MUX WITH FAN OUT BUFFERS
GENERAL DESCRIPTION
S3053
S3053
FEATURES
• Supports 2.488 Gbit/sec – 2.7 Gbit/sec
data rates
• Fully differential for minimum
jitter accumulation
• TTL select
• High speed 50Ω source terminated outputs
• 0.84 W typical power dissipation
• 3.3 V power supply
• 52 Pin TQFP/TEP
The S3053 is a high performance quad mux with fan
out buffers. It is designed to minimize jitter accumu-
lation by providing a high bandwidth fully differential
signal path. It can be used to switch OC-48 (with
FEC) data signals in Dense Wavelength Division
Multiplexer designs and other high speed serial
switch designs.
The chip is designed using four 2:1 multiplexers. It
can be used to fan out and/or multiplex high speed
clock and data signals. The S3053 is compatible
with the AMCC clock recovery, MUX/DEMUX and
Crosspoint Switch products (up to 2.7 GHz). This
allows signal integrity to be maintained throughout
the system design.
The primary AC parameter of importance is the de-
terministic jitter or data eye degradation inserted by
the crosspoint. The design minimizes jitter accumu-
lation by using high bandwidth, low skew fully differ-
ential circuits. This provides for symmetric rise and
fall delays as well as noise rejection.
Figure 1. S3053 Block Diagram
SELA
SELB
INA0P
INA0N
0
MUX
A
INA1P
INA1N
1
OUTB0P
OUTB0N
OUTB1P
0
MUX
B
1
OUTB1N
OUTC0P
OUTC0N
0
MUX
C
1
0
MUX
D
1
SELC
SELD
IND0P
IND0N
OUTC1P
OUTC1N
IND1P
IND1N
October 10, 2000 / Revision D
1
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
