SONET/SDH/ATM OC-48 1:8 RECEIVER
S3042
Table 13. AC Receiver Timing Characteristics
Symbol Description
Min
40
Max
60
Units
%
POCLK Duty Cycle
tPPOUT
tSPOUT
tHPOUT
tSRSD
POCLK Low to POUT [7:0] Valid Prop. Delay
POUT[7:0] and FP Set-up Time w.r.t. POCLK
POUT[7:0] and FP Hold Time w.r.t. POCLK
RSD/LSD Set-up Time w.r.t. RSCLK/LSCLK
RSD/LSD Hold Time w.r.t. RSCLK/LSCLK
LLCLK Duty Cycle
-500
1
+500
ps
ns
1
ns
75
ps
tHRSD
75
ps
40
60
100
55
%
tPLLD
LLCLK Low to LLD Valid Propagation Delay
RSCLK/LSCLK Duty Cycle
-100
45
ps
%
Low Swing CML Output Rise/Fall Time
20 to 80% 50Ω to VCC Load
150
ps
tSLLD
tHLLD
LLD Setup Time w.r.t. LLCLK
LLD Hold Time w.r.t. LLCLK
100
100
ps
ps
Figure 7. Output Timing Diagram
POCLK
tP
tS
tH
POUT
POUT
POUT
POUT[7:0], FP
Notes on LVDS Output Timing:
1. Timing is measured from the cross-over point of the reference signal to the cross-over point of the output.
Figure 8. Receiver Input Timing Diagram
RSCLKP/LSCLKP
tS
tH
RSD
RSD
RSD/LSD
Notes on High-Speed LVPECL Input Timing:
1. Timing is measured from the cross-over point of the reference signal to the cross-over point of the input.
Figure 9. LLD Output Timing
LLCLKP
tHLLD
tSLLD
tPLLD
LLD
1. Timing is measured from the cross-over point of the reference signal to the cross-over point of the output.
June 24, 1999 / Revision E
13
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
