S3028B 参数 Datasheet PDF下载

S3028B AND HONEYWELL OPTICS HFM2553-001 APPLICATION NOTE

Parts List

S3028B

The following is a parts list that is a recommendation to the designer to implement the circuit in Figure 2.

QTY

1

1

2

5

11

8

1

1

1

1

1

1

1

Part # or equivalent

Description

Resistor, 127 W, 10%, 1/8W, 805 or 603 package size

Resistor, 82 W, 10%, 1/8W, 805 or 603 package size

Resistor, 51 W, 10%, 1/8W, 805 or 603 package size

Resistor, 100 W, 10%, 1/8W, 805 or 603 package size

Resistor, 330 W, 10%, 1/8W, 805 or 603 package size

Resistor, 33 W, 10%, 1/8W, 805 or 603 package size

Capacitor, 1.0 mf, 10%, X7R, 16V, Surface Mount package

Capacitor, 0.01 mf, 10%, X7R, 16V, Surface Mount package

SONET/SDH/ATM OC-3/OC-12 Transceiver

SONET/SDH Clock Recovery Unit

PMC SUNI-622

Honeywell 5V Fiber Optic 1 x 9 Transceiver

PECL Oscillator

S3028B

S3027

PM5355

HFM2553-001

Theory of Operation

1. The S3027 extracts the clock and re-times the data from the received differential PECL serial data input

(SERDATIP/N) coming from the Honeywell Fiber Optic Receiver (F/O Rx) when the Signal Detect (SD) is a

PECL high level. When Signal Detect (SD) is at a PECL Low level, the Phase Lock Loop (PLL) will be forced

to lock to the TTL Reference (TTL REF).

2. The S3028B receives the OC-12/STM-4 (622.08 Mbps) scrambled NRZ data signals on the serial data stream

(RSDP/N) PECL inputs. These inputs are clocked into the S3028B by the Receive Serial Clock (RSCLKP/N)

PECL inputs. This clock is used by the receive section as the master clock to perform framing and

deserialization functions.

3. After the data is received, the Frame and Byte Boundary Detection circuitry searches the incoming data for

three consecutive A1 bytes followed by three consecutive A2 bytes. Framing pattern detection is enabled and

disabled by the Out-of-Frame (OOF) TTL input of the S3028B and the output of the PMC PM5355. The frame

boundary is reported on the Frame Pulse (FP) TTL output when any 48-bit pattern matching the framing

pattern is detected on the incoming data stream.

4. The serial-bit data stream is then converted into a byte-serial data format for output onto the TTL Parallel

Output Data Bus (POUT[7:0]). The byte-serial data is clocked out of the S3028B and into the PMC PM5355

with the TTL Parallel Output Clock (POCLK) out of the S3028B.

5. The byte-serial data is output from the PMC PM5355 into the S3028B TTL Parallel Data Input Bus (PIN[7:0])

and is sampled by the TTL Parallel Input Clock (PICLK) of the S3028B. This clock is generated by the

S3028B TTL Parallel Clock (PCLK) which is fed into the PM5355 as the Transmit Clock (TCLK) and then

back into the PICLK input of the S3028B.

6. The byte-serial data is then converted to bit-serial data and output through the PECL transmit serial data

(TSDP/N) connections to the Honeywell Fiber Optic Transmitter (F/O Tx).

7. If the incoming serial-bit data stream is lost (when SD is LOW), the Lock Detect circuit internal to the S3027

substitutes the external reference clock for the missing data stream clocking signal. This substitution of

reference timing source is helpful to supply a continuous timing signal for the follow-on devices and system

operation even though valid, received data does not exist. This switch over is a smooth transition with no

noticeable phase shift.

3