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DEVICE SPECIFICATION
SONET/SDH/ATM CLOCK RECOVERY UNIT
BiCMOS PECL CLOCK GENERATOR UNIT
SONET/SDH/ATM CLOCK RECOVERY
GENERAL DESCRIPTION
S3025
S3025
FEATURES
• Complies with ANSI, Bellcore, and ITU-T
specifications for jitter tolerance,
jitter transfer and jitter generation
• On-chip high frequency PLL with internal
loop filter for clock recovery
• Supports clock recovery for OC-12/STM-4
(622.08 Mbit/s) NRZ data
• 12.96 MHz reference frequency
• Lock detect—monitors run length and frequency
• 350mW typical power dissipation
• Low-jitter PECL interface
• On-chip crystal oscillator allows use of low cost
reference crystal
• Micro-power Bipolar technology
• 5V supply
• Available in die form or 20 TSSOP package
The function of the S3025 clock recovery unit is to
derive high speed timing signals for SONET/SDH-
based equipment. The S3025 is implemented using
AMCC’s proven Phase Locked Loop (PLL) technology.
The S3025 receives an OC-12/STM-4 scrambled NRZ
signal and recovers the clock from the data. The chip
outputs a differential PECL bit clock and retimed data.
The S3025 utilizes an on-chip PLL which consists of
a phase detector, a loop filter, and a voltage con-
trolled oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the serial data input. A loop filter converts
the phase detector output into a smooth DC voltage,
and the DC voltage is input to the VCO whose fre-
quency is varied by this voltage. A block diagram is
shown in Figure 2.
Figure 1. System Block Diagram
8
Transceiver
Controller
8
S3028
Fiber
Optic
Module
2x9
S3025
Fiber
Optic
Module
2x9
S3025
8
Transceiver
Controller
S3028
8
1
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
