SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
RECEIVER FRAMING
S3017/S3018
Figure 12 shows a typical reframe sequence in which
a byte realignment is made. The frame and byte
boundary detection is enabled by the rising edge of
OOF and remains enabled while OOF is high. Re-
alignment occurs upon receipt of the first A1 byte.
The frame boundary is recognized upon receipt of
the third A2 byte, which is the first data byte to be
reported with the correct byte alignment on the out-
going data bus (POUT[7:0]). Concurrently, the frame
pulse is set high for one POCLK cycle.
are correct, as shown in Figure 13. Since at least one
framing pattern has been detected since the rising
edge of OOF, boundary detection is disabled when
OOF is set low.
The frame and byte boundary detection block is ac-
tivated by the rising edge of OOF, and stays active
until the first FP pulse or until OOF goes low, which-
ever occurs last. Figure 13 shows a typical OOF
timing pattern which occurs when the S3018 is con-
nected to a down stream section terminating device.
OOF remains high for one full frame after the first FP
pulse. The frame and byte boundary detection block
is active until OOF goes low.
When interfacing with a section terminating device, the
OOF input remains high for one full frame after the
first frame pulse while the section terminating device
verifies internally that the frame and byte alignment
Figure 14 shows the frame and byte boundary detec-
tion activation by a rising edge of OOF, and
deactivated by the first FP pulse.
Figure 12. Frame and Byte Detection
NOTE 1: Range of input to output delay can be 1.5 to 2.5 POCLK cycles
Figure 13. OOF Operation Timing with
PM5312 STTX or PM5355 SUNI-622
Figure 14. Alternate OOF Timing
BOUNDARY DETECTION ENABLED
BOUNDARY DETECTION ENABLED
OOF
OOF
FP
FP
19
December 10, 1999 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
