S3015/S3016
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
Table 2. S3015/S3016 Clock Recovery Mode Performance Specifications
Parameter
Min
Typ
Max
Units
Condition
Nominal VCO
Center Frequency
622.08
MHz
Given REFCKIN = VCO ÷ 32
OC–3/STS–3
Lock Range
+8, -12
%
With respect to fixed reference
frequency
With device already powered up
and valid REFCLK
1
Acquisition Lock Time
64
70
µsec
Reference Clock
Input Duty Cycle
30
% of UI
Reference Clock Rise &
Fall Times
5.0
ns
10% to 90% of amplitude
PECL Output Rise & Fall
Times
10% to 90%, 50Ω load,
5 pf cap
850
100
ps
Reference Clock
Frequency Tolerance
-100
100
ppm
tP
SER
SERCLKOP Falling to
SERDATO Valid Prop
Delay
500
ps
See Figure 13
1. Specification based on design values. Not tested.
Table 3. S3015 Clock Synthesis Mode Performance Specifications
Parameter
Min
Typ
Max
Units
Condition
PECL Data Output Jitter
(S3015 SERDATOP/N)
OC–3/STS–3
In CSU mode, given
64
32
ps (rms)
• 56 ps rms jitter on
REFCKIN in 12KHz to
1 MHz band
• 28 ps rms jitter on
REFCKIN in 12KHz to
1 MHz band
E4–STS–3 CMI
Reference Clock
Frequency Tolerance
Clock Synthesis
Required to meet SONET output
jitter generation specification
-20
+20
ppm
(1)
Table 4. Electrical Characteristics for Transformer Driver
(VCC = +5V, TA = +25°C, input AC coupled unless otherwise noted.)
Parameter
Min
Typ
155
Max
Units
Condition
270 Ω || 3pF load
Operating Frequency
MHz
(2)
VSWR
1.3:1
1.5:1
75 Ω A.C. Coupled Termination
1. For output waveform characteristics, see Figures 8 and 9.
2. Up to 250 MHz.
16
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
