E4 FRAMING
BLOCK DESCRIPTIONS
Input Register:
15-bit register which holds all the
possible positions of the unframed data. The bit
position of the data in this register is dependent on
the random alignment of the data outputs of the
S3006.
8:1 Multiplexers:
These eight multiplexers select the
data alignment to be clocked into the data register.
Frame Detect:
These are 8 wide decoders which
decode the 111110100000 E4 framing pattern. The
inputs are connected to each of the eight possible
locations of the framing pattern.
Multiplexer Select Logic:
This block takes in the
results of all the decoder blocks and outputs the cor-
rect 8:1 multiplexer select values.
Data Register:
This block contains the correctly
framed data after frame alignment has occurred.
Figure 2. Detailed Schematics of E4 Framing Circuit
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