S2091A 参数 Datasheet PDF下载

S2091

2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP

Input Structures

Two input structures exist in this part; TTL and high speed, differential inputs. The LVTTL inputs will interface

with any LVTTL outputs. The high speed, differential inputs can be AC coupled per the FC-PH specification.

Therefore, the high speed, differential input buffers are biased at Vcc -0.65V. Refer to Figure 7 for high speed

differential input termination.

Figure 7. Input Termination

Biased at Vcc -0.65V

S2091

100

Ω

Figure 8. Output

VCC

50Ω

50Ω

Backplane

S2091

GND

8