S2061
S2061 OVERVIEW
The S2061 transceiver performs encoding/decoding
parallel-to-serial and serial-to-parallel conversion and
framing functions to implement a Serial Backplane
interface. Operation of the S2061 chip is straightfor-
ward, as depicted in Figure 2. The sequence of
operations is as follows:
Transmitter
1. 8-bit parallel input
2. 8B/10B encoding
3. Parallel-to-serial conversion
4. Serial output
Receiver
1. Clock and data recovery from serial input
2. Serial-to-parallel conversion
3. Frame detection
4. 10B/8B decoding
5. 8-bit parallel output
SERIAL BACKPLANE TRANSCEIVER
Internal clocking and control functions are transparent
to the user. Details of data timing can be seen in Figures
6, 7, 8.
A lock detect feature is provided for the receive PLL.
The LOCKDET output indicates that the PLL is locked
to the data stream.
Loopback Modes
Local loopback mode is supported by the chip. Local
loopback provides capability for performing offline test-
ing of the interface to ensure the integrity of the serial
channel before enabling the transmission medium. It
also allows for system diagnostics. (See the section
Other Operating Modes.)
Figure 2. Functional Block Diagram
TX [0:7]
TK [0,1]
FRAME
KGEN
8
2
D
Q
Input
Latch
8B10B
Encoder
10
SHIFT
REGISTER
TXP
TXN
TXTESTN
TBC
PLL CLOCK
MULTIPLIER
F0 = F1 X 10
WORDCLK
LOCKDET
D
RXP
RXN
TP
TN
SDTTL
SDPECL
SHIFT
REGISTER
10
8B10B
Decoder
8
D
Q
2:1
PLL CLOCK
RECOVERY
BITCLK
8
EWRAP
CONTROL
LOGIC
EN_CDET
RX[0:7]
KFLAG
BYTERR
RK[0,1]
FP
COM_DET
DETECT
LOGIC
RBC1
RBC0
2
February 2, 1999 / Revision C
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
