GIGABIT ETHERNET TRANSCEIVER
S2060
Figure 10. Transmitter Timing
TBC
TX[0-9]
T1
T2
SERIAL DATA OUT
Table 8. S2060 Transmitter Timing
Parameters
Description
Data Setup w.r.t. TBC
Data Hold w.r.t. TBC
Serial Data Rise and Fall
Min
Max Units
Conditions
T1
T2
1.2
-
-
ns
ns
ps
See Note 1.
0.25
-
T
SDR, TSDF
270
20% - 80%, tested on sample basis.
Peak-to-peak, measured on sample
basis. Measured with ±K28.5 or 27-1
pattern at 1.25 GHz.
Serial Data Output total jitter
(p-p)
TJ
-
-
192
80
ps
ps
Peak-to-peak, tested on a sample
basis. Measured with ±K28.5 pattern
at 1.25 GHz.
Serial Data Output
deterministic jitter (p-p)
TDJ
1. All AC measurements are made from the reference voltage level of the clock (+1.4 V) to the valid input or output data
levels (+.8 V or +2.0 V).
Figure 11. Receiver Timing Full Rate Mode (RATEN Active)
SERIAL DATA IN
RBC0
RBC1
comma
RX[9-0]
T3 T4
T3 T4
SKEW
March 7, 2001 / Revision H
17
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
