GIGABIT ETHERNET CHIPSET
Reference Clock Input
The reference clock input must be supplied with a PECL
single-ended AC coupled crystal clock source at
±100
PPM
tolerance. See Table 3 for reference clock frequencies.
Framing
The S2047 provides SYNC character recognition and
data word alignment of the TTL level compatible out-
put data bus. During the data realignment process,
the RCLKN phase will be adjusted. No glitches will
occur in the RCLKN signal due to the realignment. In
systems where the SYNC detect function is undes-
ired, a LOW on the SYNCEN input disables the SYNC
function and the data will be “un-framed.”
When framing is disabled by low SYNCEN, the S2047
simply achieves bit synchronization and begins to de-
liver parallel output data words whenever it has
received full transmission words. No attempt is made
to synchronize on any particular incoming character.
The SYNC output signal will go high whenever a K28.5
character (positive disparity) is present on the parallel
data outputs. The SYNC output signal will be low at
all other times. This is true whether the S2047 is
operating in 10-bit mode or in 20-bit mode.
Lock Detect
S2046/S2047
The S2047 lock detect function indicates the state of
the phase-locked loop (PLL) clock recovery unit. The
PLL will indicate lock after the start of receiving serial
data inputs. If the serial data inputs have an instanta-
neous phase jump (from a serial switch, for example)
the PLL will not indicate an out-of-lock state, but will
recover the correct phase alignment within 250 bit
times. If a run length of 64 bits is exceeded, or if the
transition density is less than 12%, the loop will be
declared out of lock and will attempt to re-acquire bit
synchronization. When lock is lost, the PLL will shift
from the serial input data to the reference clock, so
that correct frequency downstream clocking will be
maintained.
In any transfer of PLL control from the serial data to
the reference clock, the RCLK/RCLKN output remains
phase continuous and glitch free, assuring the integ-
rity of downstream clocking.
Start-Up Procedure
The clock recovery PLL requires an initilization pro-
cedure to correctly achieve lock on the serial data
inputs. At power-up or loss of lock, the PLL must first
acquire frequency lock to the local reference clock.
This can be accomplished connecting the LOCK_REF
pin to a 10 ms reset signal. If this is not possible, the
PLL can also be initialized by guaranteeing that no
data is seen at the serial data inputs for a minimum
of 10 ms upon power-up. If the serial data inputs
cannot be controlled, then the S2047 can be put into
the loopback mode and the loopback outputs of the
S2046 must be quiescent for a minimum of 10 ms
after power-up.
Table 3. Receiver Operating Modes
DWS REFSEL Data Rate Word Reference RCLK/RCLKN
(Mbps)
Width
Clock
Frequency
(Bits) Frequency
(MHz)
(MHz)
0
1
0
1
1250.0
1250.0
20
10
62.50
125.0
62.50
62.5
May 16, 2000 / Revision NC
5
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
