S2046/S2047
GIGABIT ETHERNET CHIPSET
Table 5. S2047 Pin Assignment and Descriptions (Continued)
Pin Name Level I/O
Pin #
Description
RX
RY
Diff.
9
(Externally capacitively coupled.) The received serial data inputs.
RX is the positive input, and RY is the negative input.
I
I
PECL
10
Sync Enable. Active High. (Multilevel.) When active,
enables sync detection. Detection of the sync pattern
(K28.5:0011111010, positive running disparity) will enable the
word boundary for the data to follow. When open (not connected),
REFCLK replaces internal bit clock to facilitate factory testing. In
this mode of operation, sync detection is always enabled. When
inactive, data is treated as unframed data.
Static
TTL
SYNCEN
3
Static
TTL
Reference Select. (Multilevel.) Input used to select the reference
clock frequency. (See Table 3.)
REFSEL
LOCK_REF
TTLVCC
I
I
30
50
Lock to Reference. Active Low. When active, forces the PLL to
lock to the REFCLK input and ignore the serial data inputs.
TTL
+3.3 V
or +5 V
19, 23, 36,
44
–
–
TTL Power Supply (+5 V if TTL)
TTL Ground
16, 20, 33,
41, 46
TTLGND
GND
ECLVCC
ECLVEE
AVCC
+3.3 V
GND
–
–
–
–
13, 27, 39 Core Power Supply
1, 26, 47
Core Ground
+3.3 V
GND
7
Analog Power Supply
Analog Ground
AVEE
5, 6
May 16, 2000 / Revision NC
10
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
