S2046/S2047
S2046/S2047 OVERVIEW
The S2046 transmitter and S2047 receiver provide
serialization and deserialization functions for block-
encoded data to implement a Gigabit interface.
Operation of the S2046/S2047 chips is straightfor-
ward, as depicted in Figure 2. The sequence of
operations is as follows:
Transmitter
1. 10/20-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Receiver
1. Clock and data recovery from serial input
2. Serial-to-parallel conversion
3. Frame detection
4. 10/20-bit parallel output
The 10/20-bit parallel data handled by the S2046 and
S2047 devices should be from a DC-balanced en-
coding scheme, such as the 8B/10B transmission
code, in which information to be transmitted is en-
coded 8 bits at a time into 10-bit transmission
characters.
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figure 5.
A lock detect feature is provided on the receiver, which
indicates that the PLL is locked (synchronized) to the
data stream.
Loopback
GIGABIT ETHERNET CHIPSET
Local loopback is supported by the chipset, and pro-
vides a capability for performing offline testing of the
interface to ensure the integrity of the serial channel
before enabling the transmission medium. It also al-
lows for system diagnostics.
Figure 2. Interface Diagram
Parallel
Data In
TCLK
S2046
Transmitter
Parallel
Data Out
Serial
Data
S2047
Receiver
RCLK
RCLKN
SYNC
REFCLK
Loopback
Loopback
REFCLK
Lock
Detect
S2046 TRANSMITTER
Architecture/Functional Description
The S2046 transmitter accepts parallel input data and
serializes it for transmission over fiber optic or coaxial
cable media. The S2046 is fully compliant with the
IEEE 802.3z Specification, and supports the Gigabit
Ethernet data rate of 1250 Mbit/sec.
The parallel input data word can be either 10 bits or
20 bits wide, depending upon DWS pin selection. A
block diagram showing the basic chip function is
shown in Figure 3.
Figure 3. S2046 Functional Block Diagram
OE0
OE1
10
20
10
D
Q
10
D[0:19]
2:1
TX
TY
TEST
DWS
CONTROL
LOGIC
SHIFT
REGISTER
TLX
TLY
REFSEL
DIVIDE-BY-2
REFCLK
PLL CLOCK
MULTIPLIER
F0 = F1 X 10/20
TCLK
TCLKN
2
May 16, 2000 / Revision NC
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
