GLM COMPLIANT SERIAL INTERFACE CIRCUITS
S2044/S2045
Figure 5. Functional Waveform
S
REFCLK
(Input)
2
0
PARALLEL
DATA BUS
(Input)
4
K28.5,
Byte 1
of Data
Byte 2, 3 Byte 4, 5
of Data of Data
Byte 6, 7
of Data
Byte 14,15
of Data
K28.5
Byte 16
of Data
Byte 8, 9
of Data 11 of Data 13 of Data
Byte 10, Byte 12,
4
SERIAL DATA
D2
D1
D3
D5
D4
D6
D8
D7
D9
D10 D11 D12
K28.5
D14
K28.5
D16
D13
D15
RCLK
(Output)
S
2
0
4
5
SYNC
(Output)
PARALLEL
DATA BUS
(Output)
K28.5,
Byte 1
of Data
Byte 2, 3
of Data
Byte 4, 5
of Data
Byte 6, 7
of Data
Byte 14,15
of Data
Byte 8, 9
of Data 11 of Data 13 of Data
Byte 10,
Byte 12,
Table 3. Data Mapping to 8b/10b Alphabetic Representation
First Data Byte
Second Data Byte
TX[00:19] or
0
a
1
b
2
c
3
d
4
e
5
i
6
f
7
g
8
h
9
j
10 11 12 13 14 15 16 17 18 19
RX[00:19]
8b/10b alphabetic
representation
a
b
c
d
e
i
f
g
h
j
First bit received in 20-bit mode
First bit received in 10-bit mode
S2045 RECEIVER FUNCTIONAL
DESCRIPTION
Serial/Parallel Conversion
The S2045 receiver is designed to implement the
ANSI X3T11 Fibre Channel specification receiver func-
tions. A block diagram showing the basic chip function
is provided in Figure 5.
Serial data is received on the RX, RY pins. The PLL
clock recovery circuit will lock to the data stream if
the clock to be recovered is within ±100 PPM of the
internally generated bit rate clock. The recovered clock
is used to retime the input data stream. The data is
then clocked into the serial to parallel output regis-
ters. The parallel data out can be either 10 or 20 bits
wide determined by the state of the DWS pin. The
word clock (RCLK) is synchronized to the incoming
data stream word boundary by the detection of the
fiber channel K28.5 synchronization pattern
(0011111010, positive running disparity).
Whenever a signal is present, the S2045 attempts to
achieve synchronization on both bit and transmission-
word boundaries of the received encoded bit stream.
Received data from the incoming bit stream is pro-
vided on the device’s parallel data outputs.
The S2045 accepts serial encoded data from a fiber
optic or coaxial cable interface. The serial input stream
is the result of the serialization of 8B/10B encoded
data by an FC compatible transmitter. Clock recovery
is performed on-chip, with the output data presented
to the Fibre Channel transmission layer as 10- or 20-
bit parallel data. The chip is programmable to operate
at the Fibre Channel specified operating frequencies
of 1062, 531 and 266 Mbit/s.
10-Bit/20-Bit Mode
The S2045 will operate with either 10-bit or 20-bit
parallel data outputs. This option is selectable via the
DWS pin. See Tables 3 and 4. In 10-bit mode, D10–
D19 are used and D0–D9 are driven to the logic high state.
4
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
