GLM COMPLIANT SERIAL INTERFACE CIRCUITS
S2044/S2045
S2045 Pin Assignment and Descriptions (Continued)
Pin Name Level I/O
Pin # Description
SYNCEN
Static
TTL
I
3
(Multilevel.) When HIGH, enables sync detection. Detection of
the sync pattern (K28.5:0011111010, positive running disparity)
will determine the word boundary for the data to follow. When
open (not connected), REFCLK replaces internal bit clock to
facilitate factory testing. In this mode of operation, sync
detection is always enabled. When LOW, data is treated as
unframed data.
REFSEL
RATESEL
LOCK_REF
ECLVCC
TTLGND
TTLVCC
Static
TTL
I
I
I
30
20
50
(Multilevel.) Input used to select the reference clock frequency.
(See Table 4.)
Static
TTL
(Multilevel.) Input used to select the operating speed of the
receiver. (See Table 4.)
TTL
+3.3V
GND
When LOW, forces the PLL to lock to the REFCLK input and
ignore the serial data inputs.
–
13, 27, Core Power Supply
39
–
–
16, 33, TTL Ground (0V)
41, 46
+5V or
+3.3V
19, 23, TTL Power Supply (+5V or +3.3V)
36, 44
AVCC
+3.3V
GND
GND
–
–
–
7
Analog Power Supply (+3.3V)
Analog Ground (0V)
AVEE
5, 6
ECLVEE
1, 26, 47 Core Ground (0V)
10
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
