HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
S2043 Pin Assignment and Descriptions (Continued)
S2042/S2043
Pin Name
SYNCEN
Level
Static
Multi-
Level
TTL
I/O
I
Pin #
3
Description
(Multilevel.) When HIGH, enables sync detection. Detection of
the sync pattern (K28.5:0011111010, positive running disparity)
will enable the word boundary for the data to follow. When open
(not connected), REFCLK replaces internal bit clock to facilitate
factory testing. In this mode of operation, sync detection is
always enabled. When LOW, data is treated as unframed data.
(Multilevel.) Input used to select the reference clock frequency.
(See Table 4.)
REFSEL
Static
Multi-
Level
TTL
Static
Multi-
Level
TTL
TTL
+3.3V
GND
+3.3V/
+5V
+3.3V
GND
GND
I
30
RAT ES E L
I
20
(Multilevel.) Input used to select the operating speed of the
receiver. (See Table 4.)
LOCK_REF
EC LV C C
TTLGND
TTLVCC
AVCC
AVEE
ECLVEE
I
–
–
–
–
–
–
50
13, 27,
39
16, 33,
41, 46
19, 23,
36, 44
7
5, 6
1, 26, 47
When LOW, forces the PLL to lock to the REFCLK input and
ignore the serial data inputs.
Core Power Supply
TTL Ground
TTL Power Supply (+5V if TTL)
Analog Power Supply
Analog Ground
Core Ground
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
9
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
